From: Richard Kenner Date: Sun, 16 Feb 1997 12:51:36 +0000 (-0500) Subject: (mulqihi3): Corrected. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9af35de0bc54295688fba58476b88e86cce8957a;p=gcc.git (mulqihi3): Corrected. (tst{hf,tqf}): Simplified. (movqi): Removed redundant alternative. (addqi-3,addqi-2,addqi-1): Set/Reset Bit patterns by C. Nettleton. (many patterns): Introduced operand output modifiers d,t,b,B,w. From-SVN: r13656 --- diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md index 93777b6409b..09b4211ca96 100644 --- a/gcc/config/1750a/1750a.md +++ b/gcc/config/1750a/1750a.md @@ -55,49 +55,25 @@ [(set (match_operand:QI 0 "push_operand" "=<") (match_operand:QI 1 "general_operand" "r"))] "" - "pshm r%1,r%1 ; stackptr = R%0") + "pshm r%1,r%1") (define_insn "" [(set (match_operand:HI 0 "push_operand" "=<") (match_operand:HI 1 "general_operand" "r"))] "" - "* - { - rtx new_operands[3]; - new_operands[2] = operands[0]; - new_operands[0] = operands[1]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1); - output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); - return \";\"; - } ") + "pshm r%1,r%d1") (define_insn "" [(set (match_operand:HF 0 "push_operand" "=<") (match_operand:HF 1 "general_operand" "r"))] "" - "* - { - rtx new_operands[3]; - new_operands[2] = operands[0]; - new_operands[0] = operands[1]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1); - output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); - return \";\"; - } ") + "pshm r%1,r%d1") (define_insn "" [(set (match_operand:TQF 0 "push_operand" "=<") (match_operand:TQF 1 "general_operand" "r"))] "" - "* - { - rtx new_operands[3]; - new_operands[2] = operands[0]; - new_operands[0] = operands[1]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2); - output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); - return \";\"; - } ") + "pshm r%1,r%t1") ;; stackpop (define_insn "" @@ -110,43 +86,22 @@ [(set (match_operand:HI 0 "general_operand" "=r") (match_operand:HI 1 "push_operand" ">"))] "" - "* - { - rtx new_operands[2]; - new_operands[0] = operands[0]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1); - output_asm_insn(\"popm r%0,r%1\",new_operands); - return \";\"; - } ") + "popm r%1,r%d1") (define_insn "" [(set (match_operand:HF 0 "general_operand" "=r") (match_operand:HF 1 "push_operand" ">"))] "" - "* - { - rtx new_operands[2]; - new_operands[0] = operands[0]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1); - output_asm_insn(\"popm r%0,r%1\",new_operands); - return \";\"; - } ") - + "popm r%1,r%d1") + (define_insn "" [(set (match_operand:TQF 0 "general_operand" "=r") (match_operand:TQF 1 "push_operand" ">"))] "" - "* - { - rtx new_operands[2]; - new_operands[0] = operands[0]; - new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2); - output_asm_insn(\"popm r%0,r%1\",new_operands); - return \";\"; - } ") + "popm r%1,r%t1") -;; Test operations. These shouldn't really occur for 1750: -;; all important instructions set the cc's (see NOTICE_UPDATE_CC) + +;; Test operations. (define_insn "tstqi" [(set (cc0) @@ -160,18 +115,19 @@ "" "dlr r%0,r%0 ; from tsthi") +; With 1750A floats, testing the most significant word suffices. + (define_insn "tsthf" [(set (cc0) (match_operand:HF 0 "register_operand" "r"))] "" - "dlr r%0,r%0 ; from tsthf") + "lr r%0,r%0 ; tsthf") -;; This one is happy with "roughly zero" :-) (should be improved) (define_insn "tsttqf" [(set (cc0) (match_operand:TQF 0 "register_operand" "r"))] "" - "dlr r%0,r%0 ; from tsttqf") + "lr r%0,r%0 ; tsttqf") ;; block move. @@ -267,30 +223,29 @@ (define_insn "trunchiqi2" [(set (match_operand:QI 0 "register_operand" "=r") - (truncate:QI - (match_operand:HI 1 "register_operand" "r")))] + (truncate:QI (match_operand:HI 1 "register_operand" "r")))] "" - "* - { - rtx new_operands[2]; - new_operands[0] = operands[0]; - new_operands[1] = gen_rtx (REG, QImode, REGNO(operands[1]) + 1); - output_asm_insn(\"lr r%0,r%1 ;trunchiqi2\",new_operands); - return \";\"; - } ") + "lr r%0,r%d1") + ;; zero extension instructions: not defined, GCC can synthesize ;; sign extension instructions (define_insn "extendqihi2" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )] + [(set (match_operand:HI 0 "register_operand" "=r,r") + (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m")) )] "" - "@ - lr r%0,r%1 ;extendqihi2\;dsra r%0,16 - l r%0,%1 ;extendqihi2\;dsra r%0,16 - lim r%0,%1 ;extendqihi2\;dsra r%0,16 ") + "* + if (which_alternative == 0) + { + if (REGNO (operands [0]) != REGNO (operands [1])) + output_asm_insn (\"lr r%0,r%1\", operands); + } + else + output_asm_insn (\"l r%0,%1\", operands); + return \"dsra r%0,16 ;extendqihi2\"; + ") ;; Conversions between float and double. @@ -301,16 +256,17 @@ (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))] "" "* + output_asm_insn(\"xorr r%t0,r%t0 ;extendhftqf2\", operands); + if (which_alternative == 0) { - rtx new_opnds[2]; - new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 2); - new_opnds[1] = operands[1]; - output_asm_insn(\"xorr r%0,r%0 ;extendhftqf2\",new_opnds); - if (which_alternative == 0) + if (REGNO (operands[1]) != REGNO (operands[0])) return \"dlr r%0,r%1\"; else - return \"dl r%0,%1\"; - } ") + return \";\"; + } + else + return \"dl r%0,%1\"; + ") ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits (define_insn "trunctqfhf2" @@ -362,15 +318,14 @@ ;; 16-bit moves (define_insn "movqi" - [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,r,m,m") - (match_operand:QI 1 "general_operand" "O,I,J,M,i,r,m,r,K"))] + [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,m,m") + (match_operand:QI 1 "general_operand" "O,I,J,i,r,m,r,K"))] "" "@ xorr r%0,r%0 lisp r%0,%1 lisn r%0,%J1 - lim r%0,%1 ; 'M' constraint - lim r%0,%1 ; 'i' constraint + lim r%0,%1 lr r%0,r%1 l r%0,%1 st r%1,%0 @@ -378,65 +333,18 @@ ;; 32-bit moves -; Set HIreg to constant -(define_insn "" - [(set (match_operand:HI 0 "register_operand" "=r") - (match_operand:HI 1 "immediate_operand" "i"))] - "" - "* - { - rtx new_opnds[2]; - int val = INTVAL(operands[1]); - if (val >= 0) - { - if (val <= 65535) - { - new_opnds[0] = gen_rtx(REG,QImode,REGNO(operands[0])); - new_opnds[1] = operands[1]; - output_asm_insn(\"xorr r%0,r%0 ;movhi cst->reg\",new_opnds); - REGNO(new_opnds[0]) += 1; - if (val == 0) - output_asm_insn(\"xorr r%0,r%0\",new_opnds); - else if (val <= 16) - output_asm_insn(\"lisp r%0,%1\",new_opnds); - else - output_asm_insn(\"lim r%0,%1\",new_opnds); - return \";\"; - } - } - else if (val >= -16) - return \"lisn r%0,%J1\;dsra r%0,16 ;movhi cst\"; - new_opnds[0] = gen_rtx(REG, QImode, REGNO(operands[0])); - new_opnds[1] = gen_rtx(CONST_INT,VOIDmode,(INTVAL(operands[1])) >> 16); - output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",new_opnds); - INTVAL(new_opnds[1]) = val & 0xFFFF; - REGNO(new_opnds[0]) += 1; - output_asm_insn(\"lim r%0,%1\",new_opnds); - return \";\"; - } - ") - -; Move small constant to memory, HImode (define_insn "" - [(set (match_operand:HI 0 "memory_operand" "=m") - (match_operand:HI 1 "small_nonneg_const" "K"))] + [(set (match_operand:HI 0 "general_operand" "=r,r,r,r,r,m,m") + (match_operand:HI 1 "general_operand" "O,I,J,r,m,r,K"))] "" - "* - output_asm_insn (\"stc 0,%0 ;movhi cst->mem\", operands); - return \"stc %1,%A0\"; - ") - -;; The movhi pattern. - -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=r,r,m") - (match_operand:HI 1 "general_operand" "r,m,r"))] - "register_operand (operands[0], HImode) || - register_operand (operands[1], HImode)" "@ + xorr r%0,r%0\;xorr r%d0,r%d0 + xorr r%0,r%0\;lisp r%d0,%1 + lisn r%0,1 \;lisn r%d0,%J1 dlr r%0,r%1 dl r%0,%1 - dst r%1,%0 ") + dst r%1,%0 + stc 0,%0 \;stc %1,%A0 ") (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "=g") @@ -444,37 +352,31 @@ "" " { - if (GET_CODE(operands[0]) == MEM) - { - rtx op1 = operands[1]; - if (GET_CODE(op1) == MEM - || (GET_CODE(op1) == CONST_INT - && (INTVAL(op1) < 0 || INTVAL(op1) > 15))) - operands[1] = force_reg (HImode, operands[1]); - } + rtx op1 = operands[1]; + if (GET_CODE (operands[0]) == MEM) + { + if (GET_CODE (op1) == MEM + || (GET_CODE (op1) == CONST_INT + && (INTVAL (op1) < 0 || INTVAL (op1) > 15))) + operands[1] = force_reg (HImode, operands[1]); + } + else if (GET_CODE (op1) == CONST_INT + && (INTVAL (op1) < -16 || INTVAL (op1) > 16)) + operands[1] = force_const_mem (HImode, operands[1]); }") -;; Single-Float moves are similar to HImode moves - -; Move HFmode zero to memory -(define_insn "" - [(set (match_operand:HF 0 "memory_operand" "=m") - (match_operand:HF 1 "zero_operand" "G"))] - "" - "* - output_asm_insn (\"stc 0,%0 ;movhf 0.0->mem\", operands); - return \"stc 0,%A0\"; - ") +;; Single-Float moves (define_insn "movhf" - [(set (match_operand:HF 0 "general_operand" "=r,r,m") - (match_operand:HF 1 "general_operand" "r,m,r"))] + [(set (match_operand:HF 0 "general_operand" "=r,r,m,m") + (match_operand:HF 1 "general_operand" "r,m,r,G"))] "" "@ dlr r%0,r%1 dl r%0,%1 - dst r%1,%0 ") + dst r%1,%0 + stc 0,%0 \;stc 0,%A0 ") ;; Longfloat moves @@ -611,13 +513,24 @@ ; 32-bit product (define_insn "mulqihi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (mult:HI (match_operand:QI 1 "register_operand" "%0,0,0") - (match_operand:QI 2 "general_operand" "M,r,m")))] + (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%r,r,r")) + (sign_extend:HI (match_operand:QI 2 "general_operand" "r,m,i"))))] "" - "@ - mim r%0,%1 - mr r%0,r%2 - m r%0,%2 ") + "* + if (REGNO (operands[1]) != REGNO (operands[0])) + output_asm_insn (\"lr r%0,r%1\", operands); + + switch (which_alternative) + { + case 0: + return \"mr r%0,r%2\"; + case 1: + return \"m r%0,%2\"; + case 2: + return \"mim r%0,%2\"; + } + ") + (define_insn "mulhi3" [(set (match_operand:HI 0 "register_operand" "=r,r") @@ -786,6 +699,45 @@ ;; bit-logical instructions +;; Set Bit +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=r,m") + (ior:QI (match_operand:QI 1 "general_operand" "0,0") + (match_operand:QI 2 "const_int_operand" "i,i")))] + "one_bit_set_p (INTVAL (operands [2]))" + "@ + sbr %b2,r%0 + sb %b2,%0") + +;; Reset Bit +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=r,m") + (and:QI (match_operand:QI 1 "general_operand" "0,0") + (match_operand:QI 2 "const_int_operand" "i,i")))] + "one_bit_set_p ((~INTVAL (operands [2])) & 0xffff)" + "@ + rbr %B2,r%0 + rb %B2,%0") + +;; Set Variable Bit +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=r") + (ior:QI (match_operand:QI 1 "register_operand" "0") + (lshiftrt:QI (const_int 0x8000) + (match_operand:QI 2 "register_operand" "r"))))] + "" + "svbr r%2,%r0") + +;; Reset Variable Bit +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=r") + (and:QI (match_operand:QI 1 "general_operand" "0") + (not:QI (lshiftrt:QI (const_int 0x8000) + (match_operand:QI 2 "register_operand" "r")))))] + "" + "rvbr r%2,%r0") + + ;; AND (define_insn "andqi3" @@ -900,19 +852,16 @@ (match_operand:QI 2 "nonmemory_operand" "L,r")))] "" ; the 'L' constraint is a slight imprecise... "* - if (which_alternative == 1) - return \"dslr r%0,r%2\"; - else if (INTVAL(operands[2]) <= 16) - return \"dsll r%0,%2\"; - else - { - rtx new_opnds[2]; - output_asm_insn(\"dsll r%0,16 ; ashlhi3 shiftcount > 16\",operands); - new_opnds[0] = operands[0]; - new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL(operands[2]) - 16); - output_asm_insn(\"sll r%0,%1\",new_opnds); - return \";\"; - } ") + if (which_alternative == 1) + return \"dslr r%0,r%2\"; + else if (INTVAL(operands[2]) <= 16) + return \"dsll r%0,%2\"; + else + { + output_asm_insn (\"dsll r%0,16 ; ashlhi3 shiftcnt > 16\", operands); + return \"sll r%0,%w2\"; + } + ") ;; Right shift by a variable shiftcount works by negating the shift count, @@ -964,17 +913,11 @@ (match_operand:QI 2 "immediate_operand" "L")))] "" "* - { - rtx new_opnds[2]; - int amount = INTVAL(operands[2]); - if (amount <= 16) + if (INTVAL (operands[2]) <= 16) return \"dsrl r%0,%2\"; - output_asm_insn(\"dsrl r%0,16 ; lshrhi3 shiftcount > 16\",operands); - new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1); - new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16); - output_asm_insn(\"srl r%0,%1\",new_opnds); - return \";\"; - } ") + output_asm_insn (\"dsrl r%0,16 ; lshrhi3 shiftcount > 16\", operands); + return \"srl r%d0,%w2\"; + ") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") @@ -1027,17 +970,11 @@ (match_operand:QI 2 "immediate_operand" "L")))] "" "* - { - rtx new_opnds[2]; - int amount = INTVAL(operands[2]); - if (amount <= 16) + if (INTVAL (operands[2]) <= 16) return \"dsra r%0,%2\"; - output_asm_insn(\"dsra r%0,16 ; ashrhi3 shiftcount > 16\",operands); - new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1); - new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16); - output_asm_insn(\"sra r%0,%1\",new_opnds); - return \";\"; - } ") + output_asm_insn (\"dsra r%0,16 ; ashrhi3 shiftcount > 16\", operands); + return \"sra r%d0,%w2\"; + ") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r")