From: lkcl <lkcl@web>
Date: Sun, 12 Jun 2022 14:50:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1828
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9b01bfd44845cf78ab9b569fe53906eca6855842;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index f49e567a0..0790f5fd8 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -87,7 +87,8 @@ copy the contents RA+1 into RT, but set RT+1 to zero.
 
 Also, making life easier, RT and RA are only permitted to be even
 (no overlapping can occur).  This makes RT (and RA) a "pair" exactly
-like `lq` and `stq`
+like `lq` and `stq`.  Swizzle instructions must be atomically indivisible:
+an Exception or Interrupt may not occur during the pair of Moves.
 
 **SVP64 Vectorised**