From: Luke Kenneth Casson Leighton Date: Sun, 4 Nov 2018 13:32:10 +0000 (+0000) Subject: clarify options X-Git-Tag: convert-csv-opcode-to-binary~4860 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9b05ac4c410d99d9b5438c606dab4e67ff190587;p=libreriscv.git clarify options --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 444953014..593378a0d 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2051,16 +2051,13 @@ actually specifically an "option" it is worth noting. ## RV32G Normally in standard RV32 it does not make much sense to have -RV32G, however it is automatically implied to exist in RV32+SV due to -the option for the element width to be doubled. This may be sufficient -for implementors, such that actually needing RV32G itself (which makes -no sense given that the RV32 integer register file is 32-bit) may be -redundant. - -It is a strange combination that may make sense on closer inspection, -particularly given that under the standard RV32 system many of the opcodes -to convert and sign-extend 64-bit integers to 64-bit floating-point will -be missing, as they are assumed to only be present in an RV64 context. +RV32G, The critical instructions that are missing in standard RV32 +are those for moving data to and from the double-width floating-point +registers into the integer ones, as well as the FCVT routines. + +In an earlier draft of SV, it was possible to specify an elwidth +of double the standard register size: this had to be dropped, +and may be reintroduced in future revisions. ## RV32 (not RV32F / RV32G) and RV64 (not RV64F / RV64G)