From: lkcl <lkcl@web>
Date: Sat, 1 Apr 2023 13:14:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~198
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9b08749c623fbbe339b452edd2a3d370e49ee1a0;p=libreriscv.git

---

diff --git a/openpower/sv/svp64-single.mdwn b/openpower/sv/svp64-single.mdwn
index 59623e30f..97a352415 100644
--- a/openpower/sv/svp64-single.mdwn
+++ b/openpower/sv/svp64-single.mdwn
@@ -16,4 +16,7 @@ totals 20 bits leaving 4 for a "Mode".
 * LD/ST-update needs Post-Increment, others incl. SEA (Signed Effective Address)
   another bit adds CIA for PC-relative
 
-potentially this leaves 2 bits for SUBVL.
+potentially this leaves 2 bits for SUBVL.  an advantage of that is
+that VSX could be over-ridden to have the number of PackedSIMD
+element operations redefined
+