From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 27 Jan 2020 15:46:46 +0000 (+0000)
Subject: reduce linelength <80chars
X-Git-Tag: ls180-24jan2020~328
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9b17d7bc633ca67231d1ba4c235ddf3afb4f6d15;p=ieee754fpu.git

reduce linelength <80chars
---

diff --git a/src/ieee754/fsgnj/fsgnj.py b/src/ieee754/fsgnj/fsgnj.py
index be6060bd..dbdb23d1 100644
--- a/src/ieee754/fsgnj/fsgnj.py
+++ b/src/ieee754/fsgnj/fsgnj.py
@@ -53,7 +53,7 @@ class FSGNJPipeMod(PipeModBase):
 
         # Handle opcodes 0b00 and 0b01, copying or inverting the sign bit of B
         sign = Mux(opcode[0], ~b1.s, b1.s)
-        # Handle opcodes 0b10 and 0b11, XORing the sign bits of a and b together.
+        # Handle opcodes 0b10 and 0b11, XORing sign bits of a and b together.
         # opcode 0b11 is not defined in the RISCV spec; it is handled
         # here as equivalent to opcode 0b10 (i.e. a1.s XOR b1.s)
         # because this requires slightly less logic than making it the