From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Apr 2021 16:09:34 +0000 (+0100)
Subject: add wishbone sim gtk test script
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9b21f0b1b28cf3814f553af489b795b068c52b8c;p=soc-cocotb-sim.git

add wishbone sim gtk test script
---

diff --git a/ls180/pre_pnr/run_iverilog_wb_ls180.sh b/ls180/pre_pnr/run_iverilog_wb_ls180.sh
new file mode 100755
index 0000000..15ec6fe
--- /dev/null
+++ b/ls180/pre_pnr/run_iverilog_wb_ls180.sh
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
+# Only run test in reset state as running CPU takes too much time to simulate
+make \
+  SIM=icarus \
+  TOPLEVEL=ls180 \
+  COCOTB_RESULTS_FILE=results_iverilog_ls180_wb.xml \
+  COCOTB_HDL_TIMEUNIT=100ps \
+  TESTCASE="wishbone_basic" \
+  SIM_BUILD=sim_build_iverilog_ls180 \
+  SIM_ARGS=--wave=test.ghw
+
+
+