From: Xan Date: Wed, 25 Apr 2018 10:49:11 +0000 (+0100) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~5530 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9b3266cb6159d08fb94eaeedcb1be769ecc24584;p=libreriscv.git --- diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index f139ea238..69dd23ca8 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -2,50 +2,45 @@ ## Register file -| Register | Andes ISA | Harmonised RVP ISA | -| ------------------ | ------------------------- | ------------------- | -| v0 | Hardwired zero | Hardwired zero | -| v1 | 32bit GPR or Vector[4xB or 2xH] | Predicate masks | -| v2 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] | -| v3 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] | -| v4 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] | -| v5 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] | -| v6 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] | -| v7 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xSB] | -| v8 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] | -| v9 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] | -| v10 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] | -| v11 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] | -| v12 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] | -| v13 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] | -| v14 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] | -| v15 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[4xUB] | -| v16 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] | -| v17 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] | -| v18 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] | -| v19 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] | -| v20 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] | -| v21 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] | -| v22 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] | -| v23 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xSH] | -| v24 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] | -| v25 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] | -| v26 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] | -| v27 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] | -| v28 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] | -| v29 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[2xUH] | -| v30 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[1xSW] | -| v31 | 32bit GPR or Vector[4xB or 2xH] | 32bit GPR or Vector[1xSW] | +The harmonised RVP register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16] + +| Register | Andes ISA | Harmonised RVP ISA | +| ------------------ | ------------------------- | ------------------- | +| v0 | Hardwired zero | Hardwired zero | +| v1 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate masks | +| v2 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | +| v3 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | +| v4 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | +| v5 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | +| v6 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | +| v7 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8] | +| v8 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | +| v9 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | +| v10 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | +| v11 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | +| v12 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | +| v13 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | +| v14 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | +| v15 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | +| ------------------ | ------------------------- | ------------------- | +| v16 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | +| v17 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | +| v18 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | +| v19 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | +| v20 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | +| v21 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | +| v22 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | +| v23 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | +| v24 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | +| v25 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | +| v26 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | +| v27 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | +| v28 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | +| v29 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] | +| v30 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] | +| v31 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] | - -| RADD16 rt, ra, rb | Signed Halving add | RADD (r16 <= rt,ra,rb <= r23), mm=00| -| URADD16 rt, ra, rb | Unsigned Halving add | RADD (r24 <= rt,ra,rb <= r29), mm=00| -| KADD16 rt, ra, rb | Signed Saturating add | VADD (r16 <= rt,ra,rb <= r23), mm=01| -| UKADD16 rt, ra, rb | Unsigned Saturating add | VADD (r24 <= rt,ra,rb <= r29), mm=01| -| SUB16 rt, ra, rb | Subtract | VSUB (r16 <= rt,ra,rb <= r29), mm=00| -| RSUB16 rt, ra, rb | Signed Halving sub | RSUB (r16 <= rt,ra,rb <= r23), mm=00| - ## 16-bit Arithmetic | Andes Mnemonic | 16-bit Instruction | Harmonised RVP Equivalent |