From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 Nov 2021 14:08:05 +0000 (+0000)
Subject: use Pipeline API o_ready instead of explicit core busy_o signal
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9b64158952aa9633a23b06c6e9fb21bae5d32e4a;p=soc.git

use Pipeline API o_ready instead of explicit core busy_o signal
converting core.py to Pipeline API
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 67337460..a0c4a816 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -111,12 +111,10 @@ class CoreInput:
 
 class CoreOutput:
     def __init__(self):
-        self.busy_o = Signal(name="corebusy_o", reset_less=True)
         # start/stop and terminated signalling
         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 
     def eq(self, i):
-        self.busy_o.eq(i.busy_o)
         self.core_terminate_o.eq(i.core_terminate_o)
 
 
@@ -255,6 +253,9 @@ class NonProductionCore(ControlBase):
         comb, sync = m.d.comb, m.d.sync
         fus = self.fus.fus
 
+        # indicate if core is busy
+        busy_o = Signal(name="corebusy_o", reset_less=True)
+
         # enable-signals for each FU, get one bit for each FU (by name)
         fu_enable = Signal(len(fus), reset_less=True)
         fu_bitdict = {}
@@ -274,7 +275,7 @@ class NonProductionCore(ControlBase):
         counter = Signal(2)
         with m.If(counter != 0):
             sync += counter.eq(counter - 1)
-            comb += self.o.busy_o.eq(1)
+            comb += busy_o.eq(1)
 
         with m.If(self.i.ivalid_i): # run only when valid
             with m.Switch(self.i.e.do.insn_type):
@@ -284,7 +285,7 @@ class NonProductionCore(ControlBase):
 
                 with m.Case(MicrOp.OP_NOP):
                     sync += counter.eq(2)
-                    comb += self.o.busy_o.eq(1)
+                    comb += busy_o.eq(1)
 
                 with m.Default():
                     # connect up instructions.  only one enabled at a time
@@ -299,12 +300,15 @@ class NonProductionCore(ControlBase):
                             comb += fu.oper_i.eq_from(do)
                             #comb += fu.oper_i.eq_from_execute1(e)
                             comb += fu.issue_i.eq(self.i.issue_i)
-                            comb += self.o.busy_o.eq(fu.busy_o)
+                            comb += busy_o.eq(fu.busy_o)
                             # rdmask, which is for registers, needs to come
                             # from the *main* decoder
                             rdmask = get_rdflags(self.i.e, fu)
                             comb += fu.rdmaskn.eq(~rdmask)
 
+        # set ready/valid signalling.  if busy, means refuse incoming issue
+        comb += self.p.o_ready.eq(~busy_o)
+
         return fu_bitdict
 
     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 77a4f2a5..d208e1c2 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -866,7 +866,7 @@ class TestIssuerInternal(Elaboratable):
         pdecode2 = self.pdecode2
 
         # temporaries
-        core_busy_o = core.o.busy_o                 # core is busy
+        core_busy_o = ~core.p.o_ready                # core is busy
         core_ivalid_i = core.i.ivalid_i             # instruction is valid
         core_issue_i = core.i.issue_i               # instruction is issued
         insn_type = core.i.e.do.insn_type           # instruction MicroOp type
@@ -989,7 +989,8 @@ class TestIssuerInternal(Elaboratable):
             comb += dbg_rst.eq(ResetSignal())
 
         # busy/halted signals from core
-        comb += self.busy_o.eq(core.o.busy_o)
+        core_busy_o = ~core.p.o_ready                # core is busy
+        comb += self.busy_o.eq(core_busy_o)
         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 
         # temporary hack: says "go" immediately for both address gen and ST