From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 May 2020 16:33:40 +0000 (+0100)
Subject: code-shuffle
X-Git-Tag: div_pipeline~1109
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9ba4986f9e61095169b8f2c8c34ffed069e54923;p=soc.git

code-shuffle
---

diff --git a/src/soc/cr/main_stage.py b/src/soc/cr/main_stage.py
index c6f92798..67bd78ed 100644
--- a/src/soc/cr/main_stage.py
+++ b/src/soc/cr/main_stage.py
@@ -36,7 +36,6 @@ class CRMainStage(PipeModBase):
         op = self.i.ctx.op
         xl_fields = self.fields.FormXL
         xfx_fields = self.fields.FormXFX
-
         # default: cr_o remains same as cr input unless modified, below
         cr_o = Signal.like(self.i.cr)
         comb += cr_o.eq(self.i.cr)
@@ -55,30 +54,11 @@ class CRMainStage(PipeModBase):
             comb += cr_o[31-i].eq(cr_out_arr[i])
             comb += cr_out_arr[i].eq(cr_arr[i])
 
-        # Ugh. mtocrf and mtcrf have one random bit differentiating
-        # them. This bit is not in any particular field, so this
-        # extracts that bit from the instruction
-        move_one = Signal(reset_less=True)
-        comb += move_one.eq(self.i.ctx.op.insn[20])
-
-        # crand/cror and friends get decoded to the same opcode, but
-        # one of the fields inside the instruction is a 4 bit lookup
-        # table. This lookup table gets indexed by bits a and b from
-        # the CR to determine what the resulting bit should be.
-
-        # Grab the lookup table for cr_op type instructions
-        lut = Array([Signal(name=f"lut{i}") for i in range(4)])
-        # There's no field, just have to grab it directly from the insn
-        for i in range(4):
-            comb += lut[i].eq(self.i.ctx.op.insn[6+i])
-
         # Generate the mask for mtcrf, mtocrf, and mfocrf
-        fxm = Signal(xfx_fields.FXM[0:-1].shape())
-        comb += fxm.eq(xfx_fields.FXM[0:-1])
-
         # replicate every fxm field in the insn to 4-bit, as a mask
+        FXM = xfx_fields.FXM[0:-1]
         mask = Signal(32, reset_less=True)
-        comb += mask.eq(Cat(*[Repl(fxm[i], 4) for i in range(8)]))
+        comb += mask.eq(Cat(*[Repl(FXM[i], 4) for i in range(8)]))
 
         #################################
         ##### main switch statement #####
@@ -88,30 +68,32 @@ class CRMainStage(PipeModBase):
             with m.Case(InternalOp.OP_MCRF):
                 # MCRF copies the 4 bits of crA to crB (for instance
                 # copying cr2 to cr1)
-
-                # The destination CR
-                print ("xl", xl_fields)
-                bf = Signal(xl_fields.BF[0:-1].shape())
-                comb += bf.eq(xl_fields.BF[0:-1])
-                # the source CR
-                bfa = Signal(xl_fields.BFA[0:-1].shape())
-                comb += bfa.eq(xl_fields.BFA[0:-1])
+                BF = xl_fields.BF[0:-1]   # destination CR
+                BFA = xl_fields.BFA[0:-1] # source CR
 
                 for i in range(4):
-                    comb += cr_out_arr[bf*4 + i].eq(cr_arr[bfa*4 + i])
+                    comb += cr_out_arr[BF*4 + i].eq(cr_arr[BFA*4 + i])
 
             ##### crand, cror, crnor etc. #####
             with m.Case(InternalOp.OP_CROP):
+                # crand/cror and friends get decoded to the same opcode, but
+                # one of the fields inside the instruction is a 4 bit lookup
+                # table. This lookup table gets indexed by bits a and b from
+                # the CR to determine what the resulting bit should be.
+
+                # Grab the lookup table for cr_op type instructions
+                lut = Array([Signal(name=f"lut{i}") for i in range(4)])
+                # There's no field, just have to grab it directly from the insn
+                for i in range(4):
+                    comb += lut[i].eq(self.i.ctx.op.insn[6+i])
+
                 # Get the bit selector fields from the instruction
-                bt = Signal(xl_fields.BT[0:-1].shape())
-                ba = Signal(xl_fields.BA[0:-1].shape())
-                bb = Signal(xl_fields.BB[0:-1].shape())
-                comb += bt.eq(xl_fields.BT[0:-1])
-                comb += ba.eq(xl_fields.BA[0:-1])
-                comb += bb.eq(xl_fields.BB[0:-1])
+                BT = xl_fields.BT[0:-1]
+                BA = xl_fields.BA[0:-1]
+                BB = xl_fields.BB[0:-1]
 
                 # Use the two input bits to look up the result in the LUT
-                comb += cr_out_arr[bt].eq(lut[Cat(cr_arr[bb], cr_arr[ba])])
+                comb += cr_out_arr[BT].eq(lut[Cat(cr_arr[BB], cr_arr[BA])])
 
             ##### mtcrf #####
             with m.Case(InternalOp.OP_MTCRF):
@@ -122,6 +104,12 @@ class CRMainStage(PipeModBase):
 
             ##### mfcr #####
             with m.Case(InternalOp.OP_MFCR):
+                # Ugh. mtocrf and mtcrf have one random bit differentiating
+                # them. This bit is not in any particular field, so this
+                # extracts that bit from the instruction
+                move_one = Signal(reset_less=True)
+                comb += move_one.eq(self.i.ctx.op.insn[20])
+
                 # mfocrf
                 with m.If(move_one):
                     comb += self.o.o.eq(self.i.cr & mask)