From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 11 Jul 2021 11:35:08 +0000 (+0100)
Subject: add SVP64REMAP Record
X-Git-Tag: xlen-bcd~300
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9babab0e4ca655d394cf4916baecf0d25ebc653b;p=openpower-isa.git

add SVP64REMAP Record
---

diff --git a/src/openpower/sv/svp64.py b/src/openpower/sv/svp64.py
index 16134e08..b892abbe 100644
--- a/src/openpower/sv/svp64.py
+++ b/src/openpower/sv/svp64.py
@@ -93,3 +93,48 @@ class SVP64SHAPE(Record):
         return [self.mode, self.skip, self.offset, self.invxyz, self.permute,
                 self.zdimsz, self.ydimsz, self.xdimsz]
 
+
+# in nMigen, Record begins at the LSB and fills upwards
+# however in OpenPOWER, numbering is MSB0.  sigh.
+class SVP64REMAP(Record):
+    layout=[
+            ("rsvd"  , 9),
+            ("men"  , 5),
+            ("mo1"    , 2),
+            ("mo0"    , 2),
+            ("mi2"    , 2),
+            ("mi1"    , 2),
+            ("mi0"    , 2),
+            ]
+
+    """SVP64 REMAP Record.
+
+    https://libre-soc.org/openpower/sv/remap/
+
+    | Field Name | Field bits | Description                            |
+    |------------|------------|----------------------------------------|
+    | MI0        | `0:1`      | 1st input register SVSHAPE(0-3) index  |
+    | MI1        | `2:3`      | 2nd input register SVSHAPE(0-3) index  |
+    | MI2        | `4:5`      | 3rd input register SVSHAPE(0-3) index  |
+    | MO0        | `6:7`      | 1st output register SVSHAPE(0-3) index |
+    | MO1        | `8:9`      | 2nd output register SVSHAPE(0-3) index |
+    | MEN        | `10:14`    | enables MI0..MO1                       |
+    | RESERVED   | `15:23`    | reserved                               |
+    """
+    def __init__(self, name=None):
+        Record.__init__(self, layout=self.layout, name=name)
+
+    @staticmethod
+    def order(permute):
+        return options[permute]
+
+    @staticmethod
+    def rorder(order):
+        return roptions[tuple(order)]
+
+    def ports(self):
+        return [self.mi0, self.mi1, self.mi2,
+                self.mo0, self.m02,
+                self.men, self.rsvd
+               ]
+