From: Chris Demetriou Date: Tue, 23 Oct 2001 19:20:28 +0000 (+0000) Subject: [opcodes/ChangeLog] X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9bb28706c4945adade7aa8c1e43e54522df58099;p=binutils-gdb.git [opcodes/ChangeLog] 2001-10-21 Chris Demetriou * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and "bltzall" as writing GPR 31 (since they do). * mips-dis.c (print_insn_arg): Calculate info->target where appropriate. (print_insn_mips): Fill in instruction info. (print_mips16_insn_arg): Remove unneded variable 'val'. Removed duplicated instruction target calculations, calculate once and print that result. Use same idiom for masking the jump segment bits as is used in print_insn_arg. [gas/testsuite/ChangeLog] 2001-10-21 Chris Demetriou * gas/mips/beq.s: Add zero words at end of instructions so that objdump will print "..." when disassembling. * gas/mips/beq.d: Update for disassembler changes which force branch delay-slot nops to be printed. * gas/mips/bge.d: Ditto. * gas/mips/bgeu.d: Ditto. * gas/mips/blt.d: Ditto. * gas/mips/bltu.d: Ditto. * gas/mips/jal-svr4pic.d: Ditto. * gas/mips/jal-xgot.d: Ditto. --- diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index bb4b5f8a1d1..b7048f5aef8 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2001-10-23 Chris Demetriou + + * gas/mips/beq.s: Add zero words at end of instructions so + that objdump will print "..." when disassembling. + * gas/mips/beq.d: Update for disassembler changes which force + branch delay-slot nops to be printed. + * gas/mips/bge.d: Ditto. + * gas/mips/bgeu.d: Ditto. + * gas/mips/blt.d: Ditto. + * gas/mips/bltu.d: Ditto. + * gas/mips/jal-svr4pic.d: Ditto. + * gas/mips/jal-xgot.d: Ditto. + 2001-10-20 H.J. Lu * gas/elf/ehopt0.s: Lose ",@progbits". diff --git a/gas/testsuite/gas/mips/beq.d b/gas/testsuite/gas/mips/beq.d index 9eb24345e4c..2a8abd5ad80 100644 --- a/gas/testsuite/gas/mips/beq.d +++ b/gas/testsuite/gas/mips/beq.d @@ -31,6 +31,7 @@ Disassembly of section .text: 0+0058 <[^>]*> beqzl a0,0+0000 0+005c <[^>]*> nop 0+0060 <[^>]*> bnezl a0,0+0000 +0+0064 <[^>]*> nop ... 0+20068 <[^>]*> j 0+0000 [ ]*20068: (MIPS_JMP|JMPADDR|R_MIPS_26) .text @@ -43,4 +44,5 @@ Disassembly of section .text: 0+2007c <[^>]*> nop 0+20080 <[^>]*> bal 0+20080 [ ]*20080: R_MIPS_PC16 external_label +0+20084 <[^>]*> nop ... diff --git a/gas/testsuite/gas/mips/beq.s b/gas/testsuite/gas/mips/beq.s index 5567f021034..b653cd0497c 100644 --- a/gas/testsuite/gas/mips/beq.s +++ b/gas/testsuite/gas/mips/beq.s @@ -26,5 +26,5 @@ text_label: b external_label bal external_label -# Round to a 16 byte boundary, for ease in testing multiple targets. - nop +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/mips/bge.d b/gas/testsuite/gas/mips/bge.d index 8ade2ad6143..26952deff8e 100644 --- a/gas/testsuite/gas/mips/bge.d +++ b/gas/testsuite/gas/mips/bge.d @@ -66,4 +66,5 @@ Disassembly of section .text: 0+00d8 <[^>]*> slt at,a1,a0 0+00dc <[^>]*> bnezl at,000000dc [ ]*dc: R_MIPS_PC16 external_label +0+00e0 <[^>]*> nop ... diff --git a/gas/testsuite/gas/mips/bgeu.d b/gas/testsuite/gas/mips/bgeu.d index 49d11303ca4..ace226e9eb4 100644 --- a/gas/testsuite/gas/mips/bgeu.d +++ b/gas/testsuite/gas/mips/bgeu.d @@ -60,4 +60,5 @@ Disassembly of section .text: 0+00c0 <[^>]*> sltu at,a1,a0 0+00c4 <[^>]*> bnezl at,000000c4 [ ]*c4: R_MIPS_PC16 external_label +0+00c8 <[^>]*> nop ... diff --git a/gas/testsuite/gas/mips/blt.d b/gas/testsuite/gas/mips/blt.d index d7670c0fdd3..fdc7c4ba38e 100644 --- a/gas/testsuite/gas/mips/blt.d +++ b/gas/testsuite/gas/mips/blt.d @@ -66,4 +66,5 @@ Disassembly of section .text: 0+00d8 <[^>]*> slt at,a1,a0 0+00dc <[^>]*> beqzl at,000000dc [ ]*dc: R_MIPS_PC16 external_label +0+00e0 <[^>]*> nop ... diff --git a/gas/testsuite/gas/mips/bltu.d b/gas/testsuite/gas/mips/bltu.d index 0e2a644fc43..f6fbfbb2aee 100644 --- a/gas/testsuite/gas/mips/bltu.d +++ b/gas/testsuite/gas/mips/bltu.d @@ -60,4 +60,5 @@ Disassembly of section .text: 0+00c0 <[^>]*> sltu at,a1,a0 0+00c4 <[^>]*> beqzl at,000000c4 [ ]*c4: R_MIPS_PC16 external_label +0+00c8 <[^>]*> nop ... diff --git a/gas/testsuite/gas/mips/jal-svr4pic.d b/gas/testsuite/gas/mips/jal-svr4pic.d index 5dc94c284a3..72eda5b2708 100644 --- a/gas/testsuite/gas/mips/jal-svr4pic.d +++ b/gas/testsuite/gas/mips/jal-svr4pic.d @@ -43,4 +43,5 @@ Disassembly of section .text: 0+006c <[^>]*> nop 0+0070 <[^>]*> lw gp,0\(sp\) 0+0074 <[^>]*> b 0+0000 +0+0078 <[^>]*> nop ... diff --git a/gas/testsuite/gas/mips/jal-xgot.d b/gas/testsuite/gas/mips/jal-xgot.d index 8792c9b8c6c..2f320d62a2f 100644 --- a/gas/testsuite/gas/mips/jal-xgot.d +++ b/gas/testsuite/gas/mips/jal-xgot.d @@ -48,4 +48,5 @@ Disassembly of section .text: 0+0074 <[^>]*> nop 0+0078 <[^>]*> lw gp,0\(sp\) 0+007c <[^>]*> b 0+0000 +0+0080 <[^>]*> nop ... diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5a474399a2c..b211d385c3b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,16 @@ +2001-10-23 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and + "bltzall" as writing GPR 31 (since they do). + + * mips-dis.c (print_insn_arg): Calculate info->target + where appropriate. + (print_insn_mips): Fill in instruction info. + (print_mips16_insn_arg): Remove unneded variable 'val'. + Removed duplicated instruction target calculations, + calculate once and print that result. Use same idiom for + masking the jump segment bits as is used in print_insn_arg. + 2001-10-20 Alan Modra * ppc-opc.c (CT): Make it an optional operand. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index a11e1c00434..feb9d946861 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -155,10 +155,9 @@ print_insn_arg (d, l, pc, info) break; case 'a': - (*info->print_address_func) - ((((pc + 4) & ~(bfd_vma) 0x0fffffff) - | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)), - info); + info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) + | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); + (*info->print_address_func) (info->target, info); break; case 'p': @@ -166,9 +165,8 @@ print_insn_arg (d, l, pc, info) delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; if (delta & 0x8000) delta |= ~0xffff; - (*info->print_address_func) - ((delta << 2) + pc + INSNLEN, - info); + info->target = (delta << 2) + pc + INSNLEN; + (*info->print_address_func) (info->target, info); break; case 'd': @@ -457,6 +455,12 @@ print_insn_mips (memaddr, word, info) info->bytes_per_chunk = INSNLEN; info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; if (op != NULL) @@ -470,6 +474,28 @@ print_insn_mips (memaddr, word, info) if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor)) continue; + /* Figure out instruction type and branch delay information. */ + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + { + if ((info->insn_type & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_jsr; + else + info->insn_type = dis_branch; + info->branch_delay_insns = 1; + } + else if ((op->pinfo & (INSN_COND_BRANCH_DELAY + | INSN_COND_BRANCH_LIKELY)) != 0) + { + if ((info->insn_type & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_condjsr; + else + info->insn_type = dis_condbranch; + info->branch_delay_insns = 1; + } + else if ((op->pinfo & (INSN_STORE_MEMORY + | INSN_LOAD_MEMORY_DELAY)) != 0) + info->insn_type = dis_dref; + (*info->fprintf_func) (info->stream, "%s", op->name); d = op->args; @@ -486,6 +512,7 @@ print_insn_mips (memaddr, word, info) } /* Handle undefined instructions. */ + info->insn_type = dis_noninsn; (*info->fprintf_func) (info->stream, "0x%x", word); return INSNLEN; } @@ -1006,7 +1033,6 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) else { bfd_vma baseaddr; - bfd_vma val; if (branch) { @@ -1049,9 +1075,8 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) baseaddr = memaddr - 2; } } - val = (baseaddr & ~((1 << shift) - 1)) + immed; - (*info->print_address_func) (val, info); - info->target = val; + info->target = (baseaddr & ~((1 << shift) - 1)) + immed; + (*info->print_address_func) (info->target, info); } } break; @@ -1060,9 +1085,9 @@ print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) if (! use_extend) extend = 0; l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); - (*info->print_address_func) (((memaddr + 4) & 0xf0000000) | l, info); + info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; + (*info->print_address_func) (info->target, info); info->insn_type = dis_jsr; - info->target = ((memaddr + 4) & 0xf0000000) | l; info->branch_delay_insns = 1; break; diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 578f22c7367..e2386e886a8 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -185,7 +185,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, -{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2|T3 }, @@ -217,7 +217,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, -{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 },