From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Jan 2024 15:53:19 +0000 (+0000)
Subject: improve debug output in ISACaller, for ".long xyzabcdef"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9bb49bcf65f1327b5bc727acd7094fc00a3932e7;p=openpower-isa.git

improve debug output in ISACaller, for ".long xyzabcdef"
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 0488f416..d4be4671 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2047,7 +2047,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             log("    %s sim-execute" % dbg, hex(self._pc), code)
         opname = code.split(' ')[0]
         try:
-            yield from self.call(opname)         # execute the instruction
+            asmop = yield from self.call(opname) # execute the instruction
         except MemException as e:                # check for memory errors
             if e.args[0] == 'unaligned':         # alignment error
                 # run a Trap but set DAR first
@@ -2077,9 +2077,9 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             raise e                          # ... re-raise
 
         # append to the trace log file
-        self.trace(" # %s\n" % code)
+        self.trace(" # %s %s\n" % (asmop, code))
 
-        log("gprs after code", code)
+        log("gprs after insn %s - code" % asmop, code)
         self.gpr.dump()
         crs = []
         for i in range(len(self.crl)):
@@ -2213,7 +2213,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         ins_name = name.strip()  # remove spaces if not already done so
         if self.halted:
             log("halted - not executing", ins_name)
-            return
+            return name
 
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
@@ -2244,12 +2244,12 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         log("is priv", instr_is_privileged, hex(self.msr.value), PR)
         if instr_is_privileged and PR == 1:
             self.call_trap(0x700, PIb.PRIV)
-            return
+            return asmop
 
         # check halted condition
         if ins_name == 'attn':
             self.halted = True
-            return
+            return asmop
 
         # User mode system call emulation consists of several steps:
         # 1. Detect whether instruction is sc or scv.
@@ -2276,7 +2276,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
 
             # Return from interrupt
             yield from self.call("rfid", syscall_emu_active=True)
-            return
+            return asmop
         elif ((name in ("rfid", "hrfid")) and syscall_emu_active):
             asmop = "rfid"
 
@@ -2336,7 +2336,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             self.call_trap(0x700, PIb.ILLEG)
             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
                   (ins_name, asmop, self.pc.CIA.value))
-            return
+            return asmop
 
         # this is for setvl "Vertical" mode: if set true,
         # srcstep/dststep is explicitly advanced. mode says which SVSTATE to
@@ -2348,7 +2348,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         # but PowerDecoder has a pattern for nop
         if ins_name == 'nop':
             self.update_pc_next()
-            return
+            return asmop
 
         # get elwidths, defaults to 64
         xlen = 64
@@ -2408,7 +2408,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                 self.svp64_reset_loop()
                 self.update_nia()
                 self.update_pc_next()
-                return
+                return asmop
             srcstep, dststep, ssubstep, dsubstep = self.get_src_dststeps()
             pred_dst_zero = self.pred_dst_zero
             pred_src_zero = self.pred_src_zero
@@ -2420,7 +2420,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             self.pc.update(self.namespace, self.is_svp64_mode)
             log("SVP64: VL=0, end of call", self.namespace['CIA'],
                 self.namespace['NIA'], kind=LogType.InstrInOuts)
-            return
+            return asmop
 
         # for when SVREMAP is active, using pre-arranged schedule.
         # note: modifying PowerDecoder2 needs to "settle"
@@ -2621,9 +2621,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         # truncate and make the exception "disappear".
         if self.FPSCR.FEX and (self.msr[MSRb.FE0] or self.msr[MSRb.FE1]):
             self.call_trap(0x700, PIb.FP)
-            return
+            return asmop
 
         yield from self.do_nia(asmop, ins_name, rc_en, ffirst_hit)
+        return asmop
 
     def check_ffirst(self, info, rc_en, srcstep):
         """fail-first mode: checks a bit of Rc Vector, truncates VL
diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
index 3a384499..e5d23189 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
@@ -55,7 +55,7 @@ class DDFFirstTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_maxloc_1(self):
-        self.sv_maxloc([0,6,1,7])
+        self.sv_maxloc([0,6,1,2])
 
     def tst_sv_maxloc_2(self):
         self.sv_maxloc([3,4,1,5])
@@ -81,20 +81,21 @@ class DDFFirstTestCase(FHDLTestCase):
                 #"addi 5, 4, 0",             # copy m(r4) to r5
                 # VL = MIN(CTR,MAXVL=4)
                 "mtcrf 255,0",              # clear CR entirely
-                "setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
+                "setvl 2,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
                 # load VL bytes (update r4 addr) but compressed (dw=8)
                 #"addi 6, 0, 0",             # initialise r6 to zero
                 #"sv.lbzu/pi/dw=8 *6, 1(4)", # should be /lf here as well
                 # while (i<n and a[i]<=m) : i += 1
-                "sv.minmax./ff=ge/m=ge *5, *10, *4, 1", # scalar RB=RT
+                "sv.minmax./ff=ge/m=ge *5, *10, *4, 1",
                 "sv.mcrf/m=ge *4,*0", # masked-copy CR0-CR3 to CR4-CR7
-                "setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
+                "setvl 2,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
                 "sv.addi/mr/m=lt 4, *5, 0", # r4 = last non-masked value
                 "mtcrf 128, 0",       # clear CR0
-                "sv.minmax./ff=lt/m=ge/vli 4, *10, 4, 1", # scalar RB=RT
-                "sv.svstep/mr 2, 0, 6, 1",  # svstep: get vector dststep
-                "sv.creqv *16,*16,*16", # masked-copy CR0-CR3 to CR4-CR7
-                "bc 12,0, -0x3c"            # CR0 lt bit clear, branch back
+                "sv.minmax./ff=lt/m=ge 4, *10, 4, 1", # uses r4 as accumulator
+                "sv.svstep/mr 3, 0, 6, 1",  # svstep: get vector dststep
+                "sv.addi/m=1<<r3 *10, 4, 0", # put r4 into vector at r10
+                "sv.creqv *16,*16,*16", # set mask on already-tested
+                "bc 12,0, -0x44"            # CR0 lt bit clear, branch back
                 #"setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
                 #"sv.bc/all/m=ge 16, 19, -0x3c", # until r10[i]>r4 (and dec CTR)
                         ])