From: whitequark <whitequark@whitequark.org>
Date: Sun, 16 Dec 2018 17:41:11 +0000 (+0000)
Subject: back.rtlil: avoid illegal slices.
X-Git-Tag: working~204
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9bce35098f65d3653230721ce74a09a85d9e529b;p=nmigen.git

back.rtlil: avoid illegal slices.

Not sure what to do with {} [] on LHS yet--fix Yosys?
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 7f584ff..dada675 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -272,14 +272,6 @@ class _ValueCompiler(xfrm.AbstractValueTransformer):
     def on_ResetSignal(self, value):
         raise NotImplementedError # :nocov:
 
-    def on_Slice(self, value):
-        if value.start == 0 and value.end == len(value.value):
-            return self(value.value)
-        elif value.start + 1 == value.end:
-            return "{} [{}]".format(self(value.value), value.start)
-        else:
-            return "{} [{}:{}]".format(self(value.value), value.end - 1, value.start)
-
     def on_Cat(self, value):
         return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.operands])))
 
@@ -410,6 +402,21 @@ class _RHSValueCompiler(_ValueCompiler):
         else:
             raise TypeError # :nocov:
 
+    def on_Slice(self, value):
+        if value.start == 0 and value.end == len(value.value):
+            return self(value.value)
+
+        if isinstance(value.value, ast.Signal):
+            sigspec = self(value.value)
+        else:
+            sigspec = self.s.rtlil.wire(len(value.value))
+            self.s.rtlil.connect(sigspec, self(value.value))
+
+        if value.start + 1 == value.end:
+            return "{} [{}]".format(sigspec, value.start)
+        else:
+            return "{} [{}:{}]".format(sigspec, value.end - 1, value.start)
+
     def on_Part(self, value):
         raise NotImplementedError
 
@@ -433,6 +440,20 @@ class _LHSValueCompiler(_ValueCompiler):
             raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(value)))
         return wire_next
 
+    def on_Slice(self, value):
+        if value.start == 0 and value.end == len(value.value):
+            return self(value.value)
+
+        if isinstance(value.value, ast.Signal):
+            sigspec = self(value.value)
+        else:
+            raise NotImplementedError
+
+        if value.start + 1 == value.end:
+            return "{} [{}]".format(sigspec, value.start)
+        else:
+            return "{} [{}:{}]".format(sigspec, value.end - 1, value.start)
+
     def on_Part(self, value):
         raise NotImplementedError