From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Mar 2022 21:21:48 +0000 (+0000)
Subject: sort out platform IO pads for iverilog hyperram sim
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9bd0292a92ca7f1af25627778dd38c6cf90f91e1;p=ls2.git

sort out platform IO pads for iverilog hyperram sim
---

diff --git a/runsimsoc_hyperram.sh b/runsimsoc_hyperram.sh
index 02e4389..4e235d4 100755
--- a/runsimsoc_hyperram.sh
+++ b/runsimsoc_hyperram.sh
@@ -3,7 +3,7 @@ set -e
 
 LIB_DIR=./src/ecp5u
 
-HYPERRAM_DIR=./s27kl0641/model
+HYPERRAM_DIR=./hyperram_model/s27kl0641/model
 
 # create the build_simsoc/top.il file with firmware baked-in
 python3 src/ls2.py isim ./coldboot/coldboot.bin
@@ -16,8 +16,8 @@ cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v
 patch DDRDLLA.v < DDRDLLA.patch
 
 # string together the icarus verilog files and start runnin
-iverilog -Wall -g2012 -s simsoctb -o simsoc \
-        src/simsoctb.v ./top.v \
+iverilog -Wall -g2012 -s simsoc_hyperram_tb -o simsoc \
+        src/simsoc_hyperram_tb.v ./top.v \
     ${HYPERRAM_DIR}/s27kl0641.v \
     ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v \
     ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
diff --git a/src/ls2.py b/src/ls2.py
index 9c057ac..3aa51e4 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -578,10 +578,14 @@ def build_platform(fpga, firmware):
     else:
         platform = None
 
+    print ("platform", fpga, firmware, platform)
+
     # set clock frequency
     clk_freq = 70e6
     if fpga == 'sim':
         clk_freq = 100e6
+    if fpga == 'isim':
+        clk_freq = 50e6 # below 50 mhz, stops DRAM being enabled
     if fpga == 'versa_ecp5':
         clk_freq = 50e6 # crank right down to test hyperram
     if fpga == 'versa_ecp5_85':
@@ -631,8 +635,17 @@ def build_platform(fpga, firmware):
 
     # Get HyperRAM pins
     hyperram_pins = None
-    if platform is None or platform in ['isim']:
+    if platform is None:
         hyperram_pins = HyperRAMPads()
+    elif fpga in ['isim']:
+        hyperram_ios = HyperRAMResource(0, cs_n="B11",
+                                        dq="D4 D3 F4 F3 G2 H2 D2 E2",
+                                        rwds="U13", rst_n="T13", ck_p="V10",
+                                        # ck_n="D12" - for later (DDR)
+                                        attrs=Attrs(IOSTANDARD="LVCMOS33"))
+        platform.add_resources(hyperram_ios)
+        hyperram_pins = platform.request("hyperram")
+        print ("isim a7 hyperram", hyperram_ios)
     # Digilent Arty A7-100t
     elif platform is not None and fpga in ['arty_a7']:
         hyperram_ios = HyperRAMResource(0, cs_n="B11",
@@ -652,6 +665,7 @@ def build_platform(fpga, firmware):
         platform.add_resources(hyperram_ios)
         hyperram_pins = platform.request("hyperram")
         print ("versa ecp5 hyperram", hyperram_ios)
+    print ("hyperram pins", hyperram_pins)
 
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,