From: Andrew Waterman Date: Mon, 15 May 2017 15:50:57 +0000 (-0700) Subject: RISC-V: Fix SLTI disassembly X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9bdfdbf929d581cf845ffc815ae94a39d9f7b032;p=binutils-gdb.git RISC-V: Fix SLTI disassembly 2017-06-23 Andrew Waterman * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an alias; do not mark SLTI instruction as an alias. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b2e77290241..5371bbb57b3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-06-23 Andrew Waterman + + * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an + alias; do not mark SLTI instruction as an alias. + 2017-06-21 H.J. Lu * i386-dis.c (RM_0FAE_REG_5): Removed. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 0188a653f20..9914c447442 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -245,9 +245,9 @@ const struct riscv_opcode riscv_opcodes[] = {"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS }, {"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS }, {"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS }, -{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, +{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, {"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 }, -{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, +{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, {"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 }, {"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 }, {"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS },