From: Luke Kenneth Casson Leighton Date: Fri, 29 Jul 2022 12:10:33 +0000 (+0100) Subject: CARRY-add on 66000 is 1-bit (duh) X-Git-Tag: opf_rfc_ls005_v1~946 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9be948543109eda44ca7db3d7f9d0cd52a8fddf6;p=libreriscv.git CARRY-add on 66000 is 1-bit (duh) --- diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 058930ebe..c1bb977e9 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -56,4 +56,4 @@ [^34]: [Advanced matrix Extensions](https://en.wikipedia.org/wiki/Advanced_Matrix_Extensions) supports BF16 and INT8 only. Separate regfile, power-of-two "tiles". Not general-purpose at all. [^35]: Although registers may be 128-bit in NEON, SVE2, and AVX, unlike VSX there are very few (or no) actual arithmetic 128-bit operations. Only RVV and SVP64 have the possibility of 128-bit ops [^36]: Mitch Alsup's MyISA 66000 is available on request. A powerful RISC ISA with a **Hardware-level auto-vectorisation** LOOP built-in as an extension named VVM. Classified as "Vertical-First". -[^37]: MyISA 66000 has a CARRY register up to 64-bit. Repeated application of FMA or ADD (esp. within Auto-Vectored LOOPS) automatically and inherently creates big-int operations with zero effort. +[^37]: MyISA 66000 has a CARRY register up to 64-bit. Repeated application of FMA (esp. within Auto-Vectored LOOPS) automatically and inherently creates big-int operations with zero effort.