From: klehman <klehman9@comcast.net>
Date: Sat, 18 Sep 2021 11:44:01 +0000 (-0400)
Subject: added get_mem
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9bfa69243b8d2d7f9bcef284e3387c81f935ac70;p=soc.git

added get_mem
---

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index a446d415..3b7eeb20 100644
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -49,6 +49,19 @@ class HDLState(State):
         self.pcl.append(self.pc)
         log("class hdl pc", hex(self.pc))
 
+    def get_mem(self):
+        if hasattr(self.core.l0.pimem, 'lsui'):
+            hdlmem = self.core.l0.pimem.lsui.mem
+        else:
+            hdlmem = self.core.l0.pimem.mem
+            if not isinstance(hdlmem, Memory):
+                hdlmem = hdlmem.mem
+        self.mem = []
+        for i in range(hdlmem.depth):
+            value = yield hdlmem._array[i]
+            if value != 0:  # for comparison purposes
+                self.mem.append(((i*8), value))
+
 
 # add to State Factory
 state_add('hdl', HDLState)