From: whitequark <whitequark@whitequark.org>
Date: Thu, 9 Jul 2020 18:13:04 +0000 (+0000)
Subject: Revert PRs #2203 and #2244.
X-Git-Tag: working-ls180~391^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c120b89ace6c111aa4677616947d18d980b9c1a;p=yosys.git

Revert PRs #2203 and #2244.

This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15.
This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405.
This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3.
This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68.
This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index dfdb11cf0..0fdf2b516 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -747,7 +747,7 @@ module_body:
 module_body_stmt:
 	task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
 	enum_decl | struct_decl |
-	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
+	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
 
 checker_decl:
 	TOK_CHECKER TOK_ID ';' {
@@ -1331,45 +1331,36 @@ ignspec_id:
 param_signed:
 	TOK_SIGNED {
 		astbuf1->is_signed = true;
-	} | TOK_UNSIGNED {
-		astbuf1->is_signed = false;
 	} | /* empty */;
 
 param_integer:
 	TOK_INTEGER {
+		if (astbuf1->children.size() != 1)
+			frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
 		astbuf1->children.push_back(new AstNode(AST_RANGE));
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
 		astbuf1->is_signed = true;
-	}
+	} | /* empty */;
 
 param_real:
 	TOK_REAL {
+		if (astbuf1->children.size() != 1)
+			frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
 		astbuf1->children.push_back(new AstNode(AST_REALVALUE));
-	}
-
-param_logic:
-	TOK_LOGIC {
-		// SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned
-		astbuf1->is_signed = false;
-		astbuf1->is_logic = true;
-	}
+	} | /* empty */;
 
 param_range:
 	range {
 		if ($1 != NULL) {
+			if (astbuf1->children.size() != 1)
+				frontend_verilog_yyerror("integer/real parameters should not have a range.");
 			astbuf1->children.push_back($1);
 		}
 	};
 
-param_integer_type: param_integer param_signed
-param_range_type: type_vec param_signed param_range
-param_implicit_type: param_signed param_range
-
-param_integer_vector_type: param_logic param_signed param_range
-
 param_type:
-	param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type |
+	param_signed param_integer param_real param_range |
 	hierarchical_type_id {
 		astbuf1->is_custom_type = true;
 		astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
diff --git a/tests/various/integer_range_bad_syntax.ys b/tests/various/integer_range_bad_syntax.ys
deleted file mode 100644
index 4f427211f..000000000
--- a/tests/various/integer_range_bad_syntax.ys
+++ /dev/null
@@ -1,6 +0,0 @@
-logger -expect error "syntax error, unexpected" 1
-read_verilog -sv <<EOT
-module test_integer_range();
-parameter integer [31:0] a = 0;
-endmodule
-EOT
diff --git a/tests/various/integer_real_bad_syntax.ys b/tests/various/integer_real_bad_syntax.ys
deleted file mode 100644
index 942d8de77..000000000
--- a/tests/various/integer_real_bad_syntax.ys
+++ /dev/null
@@ -1,6 +0,0 @@
-logger -expect error "syntax error, unexpected TOK_REAL" 1
-read_verilog -sv <<EOT
-module test_integer_real();
-parameter integer real a = 0;
-endmodule
-EOT
diff --git a/tests/various/logic_param_simple.ys b/tests/various/logic_param_simple.ys
deleted file mode 100644
index 968564080..000000000
--- a/tests/various/logic_param_simple.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog -sv <<EOT
-module test_logic_param();
-parameter logic                 a = 0;
-parameter logic [31:0]          e = 0;
-parameter logic signed          b = 0;
-parameter logic unsigned        c = 0;
-parameter logic unsigned [31:0] d = 0;
-endmodule
-EOT
diff --git a/tests/various/signed.ys b/tests/various/signed.ys
deleted file mode 100644
index 2319a5da1..000000000
--- a/tests/various/signed.ys
+++ /dev/null
@@ -1,28 +0,0 @@
-# SV LRM A2.2.1
-
-read_verilog -sv <<EOT
-module test_signed();
-parameter integer signed  a = 0;
-parameter integer unsigned  b = 0;
-
-endmodule
-EOT
-
-design -reset
-read_verilog -sv <<EOT
-module test_signed();
-parameter logic signed [7:0] a = 0;
-parameter logic unsigned [7:0] b = 0;
-
-endmodule
-EOT
-
-design -reset
-logger -expect error "syntax error, unexpected TOK_INTEGER" 1
-read_verilog -sv <<EOT
-module test_signed();
-parameter signed integer a = 0;
-parameter unsigned integer b = 0;
-
-endmodule
-EOT