From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Thu, 9 Jul 2020 12:53:53 +0000 (+0200)
Subject: Fix counter reset condition bug
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c1ad5419d8c6c8114e8695a804de2df56ab6bf1;p=gram.git

Fix counter reset condition bug
---

diff --git a/gram/frontend/wishbone.py b/gram/frontend/wishbone.py
index ccfdec1..04502ce 100644
--- a/gram/frontend/wishbone.py
+++ b/gram/frontend/wishbone.py
@@ -17,6 +17,7 @@ class gramWishbone(Peripheral, Elaboratable):
 
         self.dw = data_width
         self._port = core.crossbar.get_native_port()
+        #self._port = core.crossbar.get_port(data_width=8, mode="read")
 
         dram_size = core.size//4
         dram_addr_width = log2_int(dram_size)
@@ -57,7 +58,7 @@ class gramWishbone(Peripheral, Elaboratable):
                 ]
                 with m.If(self._port.cmd.valid & self._port.cmd.ready):
                     m.d.sync += count.eq(count+1)
-                    with m.If(count == (ratio-1)):
+                    with m.If(count == (max(ratio, 2)-1)):
                         m.d.sync += count.eq(0)
                         with m.If(self.bus.we):
                             m.next = "Wait-Write"