From: lkcl <lkcl@web>
Date: Mon, 28 Jun 2021 08:57:18 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~707
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c383fd6f25a8f03485300859fcd5d0f2a20f55c;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index baacec2d5..060b558b9 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -9,6 +9,7 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=571>
 * <https://llvm.org/devmtg/2016-11/Slides/Emerson-ScalableVectorizationinLLVMIR.pdf>
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-loads-and-stores>
+* [[simple_v_extension/specification/ld.x]]
 
 Vectorisation of Load and Store requires creation, from scalar operations,
 a number of different modes: