From: Florent Kermarrec Date: Fri, 1 Nov 2019 10:33:43 +0000 (+0100) Subject: interconnect/csr_bus/SRAM: add mem_size check X-Git-Tag: 24jan2021_ls180~882 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c3c43c94ade654a1e386ff6dd131195dd6d63d7;p=litex.git interconnect/csr_bus/SRAM: add mem_size check Memory size is limited to 512 bytes: - CSR region size is 0x800 (4096) - default csr_data_width is 8 maximum size = 4096/8 = 512 bytes. --- diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py index dac45972..5c60aa0a 100644 --- a/litex/soc/interconnect/csr_bus.py +++ b/litex/soc/interconnect/csr_bus.py @@ -84,6 +84,9 @@ class SRAM(Module): mem = mem_or_size else: mem = Memory(data_width, mem_or_size//(data_width//8), init=init) + mem_size = int(mem.width*mem.depth/8) + if mem_size > 512: + raise ValueError("Memory too large to fit in CSR region ({} > 512 bytes)".format(mem_size)) csrw_per_memw = (mem.width + data_width - 1)//data_width word_bits = log2_int(csrw_per_memw) page_bits = log2_int((mem.depth*csrw_per_memw + 511)//512, False)