From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 17:27:07 +0000 (-0700)
Subject: Format `-pwires`
X-Git-Tag: working-ls180~1086
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c4e1c6a8fc47f44011f1f75e9493a1bc2de520d;p=yosys.git

Format `-pwires`
---

diff --git a/README.md b/README.md
index 38ca77862..0195248a0 100644
--- a/README.md
+++ b/README.md
@@ -330,7 +330,7 @@ Verilog Attributes and non-standard features
 
 - The ``parameter`` and ``localparam`` attributes are used to mark wires
   that represent module parameters or localparams (when the HDL front-end
-  is run in -pwires mode).
+  is run in ``-pwires`` mode).
 
 - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
   module to mark it as a clock buffer output, and thus prevent ``clkbufmap``