From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 09:10:53 +0000 (+0100) Subject: tidy up table X-Git-Tag: convert-csv-opcode-to-binary~4960 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c538b23f336e0dac30ea23f5c09a96a74e5d9a1;p=libreriscv.git tidy up table --- diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn index be6346c6c..6154f0e1f 100644 --- a/simple_v_extension/opcodes.mdwn +++ b/simple_v_extension/opcodes.mdwn @@ -3,227 +3,227 @@ | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|lui | rd imm20 u rv32i rv64i rv128i -|auipc | rd oimm20 u+o rv32i rv64i rv128i -|jal | rd jimm20 uj rv32i rv64i rv128i -|jalr | rd rs1 oimm12 i+o rv32i rv64i rv128i -|beq | rs1 rs2 sbimm12 sb rv32i rv64i rv128i -|bne | rs1 rs2 sbimm12 sb rv32i rv64i rv128i -|blt | rs1 rs2 sbimm12 sb rv32i rv64i rv128i -|bge | rs1 rs2 sbimm12 sb rv32i rv64i rv128i -|bltu | rs1 rs2 sbimm12 sb rv32i rv64i rv128i -|bgeu | rs1 rs2 sbimm12 sb rv32i rv64i rv128i -|lb | rd rs1 oimm12 i+l rv32i rv64i rv128i -|lh | rd rs1 oimm12 i+l rv32i rv64i rv128i -|lw | rd rs1 oimm12 i+l rv32i rv64i rv128i -|lbu | rd rs1 oimm12 i+l rv32i rv64i rv128i -|lhu | rd rs1 oimm12 i+l rv32i rv64i rv128i -|sb | rs1 rs2 simm12 s rv32i rv64i rv128i -|sh | rs1 rs2 simm12 s rv32i rv64i rv128i -|sw | rs1 rs2 simm12 s rv32i rv64i rv128i -|addi | rd rs1 imm12 i rv32i rv64i rv128i -|slti | rd rs1 imm12 i rv32i rv64i rv128i -|sltiu | rd rs1 imm12 i rv32i rv64i rv128i -|xori | rd rs1 imm12 i rv32i rv64i rv128i -|ori | rd rs1 imm12 i rv32i rv64i rv128i -|andi | rd rs1 imm12 i rv32i rv64i rv128i -|slli | rd rs1 shamt5 31..27=0 i·sh5 rv32i -|srli | rd rs1 shamt5 31..27=0 i·sh5 rv32i -|srai | rd rs1 shamt5 31..27=8 i·sh5 rv32i -|add | rd rs1 rs2 31..25=0 r rv32i rv64i rv128i -|sub | rd rs1 rs2 31..25=32 r rv32i rv64i rv128i -|sll | rd rs1 rs2 31..25=0 r rv32i rv64i rv128i -|slt | rd rs1 rs2 31..25=0 r rv32i rv64i rv128i -|sltu | rd rs1 rs2 31..25=0 r rv32i rv64i rv128i -|xor | rd rs1 rs2 31..25=0 r rv32i rv64i rv128i -|srl | rd rs1 rs2 31..25=0 r rv32i rv64i rv128i -|sra | rd rs1 rs2 31..25=32 r rv32i rv64i rv128i -|or | rd rs1 rs2 31..25=0 r rv32i rv64i rv128i -|and | rd rs1 rs2 31..25=0 r rv32i rv64i rv128i -|fence | 31..28=ignore pred succ 11..7=ignore 6..2=0x03 1..0=3 r·f rv32i rv64i rv128i -|fence.i | 31..28=ignore 27..20=ignor11..7=ignore 6..2=0x03 1..0=3 none rv32i rv64i rv128i +|lui | rd imm20 | u rv32i rv64i rv128i +|auipc | rd oimm20 | u+o rv32i rv64i rv128i +|jal | rd jimm20 | uj rv32i rv64i rv128i +|jalr | rd rs1 oimm12 | i+o rv32i rv64i rv128i +|beq | rs1 rs2 sbimm12 | sb rv32i rv64i rv128i +|bne | rs1 rs2 sbimm12 | sb rv32i rv64i rv128i +|blt | rs1 rs2 sbimm12 | sb rv32i rv64i rv128i +|bge | rs1 rs2 sbimm12 | sb rv32i rv64i rv128i +|bltu | rs1 rs2 sbimm12 | sb rv32i rv64i rv128i +|bgeu | rs1 rs2 sbimm12 | sb rv32i rv64i rv128i +|lb | rd rs1 oimm12 | i+l rv32i rv64i rv128i +|lh | rd rs1 oimm12 | i+l rv32i rv64i rv128i +|lw | rd rs1 oimm12 | i+l rv32i rv64i rv128i +|lbu | rd rs1 oimm12 | i+l rv32i rv64i rv128i +|lhu | rd rs1 oimm12 | i+l rv32i rv64i rv128i +|sb | rs1 rs2 simm12 | s rv32i rv64i rv128i +|sh | rs1 rs2 simm12 | s rv32i rv64i rv128i +|sw | rs1 rs2 simm12 | s rv32i rv64i rv128i +|addi | rd rs1 imm12 | i rv32i rv64i rv128i +|slti | rd rs1 imm12 | i rv32i rv64i rv128i +|sltiu | rd rs1 imm12 | i rv32i rv64i rv128i +|xori | rd rs1 imm12 | i rv32i rv64i rv128i +|ori | rd rs1 imm12 | i rv32i rv64i rv128i +|andi | rd rs1 imm12 | i rv32i rv64i rv128i +|slli | rd rs1 shamt5 | i·sh5 rv32i +|srli | rd rs1 shamt5 | i·sh5 rv32i +|srai | rd rs1 shamt5 | i·sh5 rv32i +|add | rd rs1 rs2 | r rv32i rv64i rv128i +|sub | rd rs1 rs2 | r rv32i rv64i rv128i +|sll | rd rs1 rs2 | r rv32i rv64i rv128i +|slt | rd rs1 rs2 | r rv32i rv64i rv128i +|sltu | rd rs1 rs2 | r rv32i rv64i rv128i +|xor | rd rs1 rs2 | r rv32i rv64i rv128i +|srl | rd rs1 rs2 | r rv32i rv64i rv128i +|sra | rd rs1 rs2 | r rv32i rv64i rv128i +|or | rd rs1 rs2 | r rv32i rv64i rv128i +|and | rd rs1 rs2 | r rv32i rv64i rv128i +|fence | | r·f rv32i rv64i rv128i +|fence.i | | none rv32i rv64i rv128i # RV64I "RV64I Base Integer Instruction Set (in addition to RV32I)" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|lwu | rd rs1 oimm12 i+l rv64i rv128i -|ld | rd rs1 oimm12 i+l rv64i rv128i -|sd | rs1 rs2 simm12 s rv64i rv128i -|slli | rd rs1 shamt6 31..27=0 i·sh6 rv64i -|srli | rd rs1 shamt6 31..27=0 i·sh6 rv64i -|srai | rd rs1 shamt6 31..27=8 i·sh6 rv64i -|addiw | rd rs1 imm12 i rv64i rv128i -|slliw | rd rs1 shamt5 31..25=0 i·sh5 rv64i rv128i -|srliw | rd rs1 shamt5 31..25=0 i·sh5 rv64i rv128i -|sraiw | rd rs1 shamt5 31..25=32 i·sh5 rv64i rv128i -|addw | rd rs1 rs2 31..25=0 r rv64i rv128i -|subw | rd rs1 rs2 31..25=32 r rv64i rv128i -|sllw | rd rs1 rs2 31..25=0 r rv64i rv128i -|srlw | rd rs1 rs2 31..25=0 r rv64i rv128i -|sraw | rd rs1 rs2 31..25=32 r rv64i rv128i +|lwu | rd rs1 oimm12 | i+l rv64i rv128i +|ld | rd rs1 oimm12 | i+l rv64i rv128i +|sd | rs1 rs2 simm12 | s rv64i rv128i +|slli | rd rs1 shamt6 | i·sh6 rv64i +|srli | rd rs1 shamt6 | i·sh6 rv64i +|srai | rd rs1 shamt6 | i·sh6 rv64i +|addiw | rd rs1 imm12 | i rv64i rv128i +|slliw | rd rs1 shamt5 | i·sh5 rv64i rv128i +|srliw | rd rs1 shamt5 | i·sh5 rv64i rv128i +|sraiw | rd rs1 shamt5 | i·sh5 rv64i rv128i +|addw | rd rs1 rs2 | r rv64i rv128i +|subw | rd rs1 rs2 | r rv64i rv128i +|sllw | rd rs1 rs2 | r rv64i rv128i +|srlw | rd rs1 rs2 | r rv64i rv128i +|sraw | rd rs1 rs2 | r rv64i rv128i # RV128I "RV128I Base Integer Instruction Set (in addition to RV64I)" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|ldu | rd rs1 oimm12 i+l rv128i -|lq | rd rs1 oimm12 i+l rv128i -|sq | rs1 rs2 simm12 s rv128i -|slli | rd rs1 shamt7 31..27=0 i·sh7 rv128i -|srli | rd rs1 shamt7 31..27=0 i·sh7 rv128i -|srai | rd rs1 shamt7 31..27=8 i·sh7 rv128i -|addid | rd rs1 imm12 i rv128i -|sllid | rd rs1 shamt6 31..26=0 i·sh6 rv128i -|srlid | rd rs1 shamt6 31..26=0 i·sh6 rv128i -|sraid | rd rs1 shamt6 31..26=16 i·sh6 rv128i -|addd | rd rs1 rs2 31..25=0 r rv128i -|subd | rd rs1 rs2 31..25=32 r rv128i -|slld | rd rs1 rs2 31..25=0 r rv128i -|srld | rd rs1 rs2 31..25=0 r rv128i -|srad | rd rs1 rs2 31..25=32 r rv128i +|ldu | rd rs1 oimm12 | i+l rv128i +|lq | rd rs1 oimm12 | i+l rv128i +|sq | rs1 rs2 simm12 | s rv128i +|slli | rd rs1 shamt7 | i·sh7 rv128i +|srli | rd rs1 shamt7 | i·sh7 rv128i +|srai | rd rs1 shamt7 | i·sh7 rv128i +|addid | rd rs1 imm12 | i rv128i +|sllid | rd rs1 shamt6 | i·sh6 rv128i +|srlid | rd rs1 shamt6 | i·sh6 rv128i +|sraid | rd rs1 shamt6 | i·sh6 rv128i +|addd | rd rs1 rs2 | r rv128i +|subd | rd rs1 rs2 | r rv128i +|slld | rd rs1 rs2 | r rv128i +|srld | rd rs1 rs2 | r rv128i +|srad | rd rs1 rs2 | r rv128i # RV32M "RV32M Standard Extension for Integer Multiply and Divide" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|mul | rd rs1 rs2 31..25=1 r rv32m rv64m rv128m -|mulh | rd rs1 rs2 31..25=1 r rv32m rv64m rv128m -|mulhsu | rd rs1 rs2 31..25=1 r rv32m rv64m rv128m -|mulhu | rd rs1 rs2 31..25=1 r rv32m rv64m rv128m -|div | rd rs1 rs2 31..25=1 r rv32m rv64m rv128m -|divu | rd rs1 rs2 31..25=1 r rv32m rv64m rv128m -|rem | rd rs1 rs2 31..25=1 r rv32m rv64m rv128m -|remu | rd rs1 rs2 31..25=1 r rv32m rv64m rv128m +|mul | rd rs1 rs2 | r rv32m rv64m rv128m +|mulh | rd rs1 rs2 | r rv32m rv64m rv128m +|mulhsu | rd rs1 rs2 | r rv32m rv64m rv128m +|mulhu | rd rs1 rs2 | r rv32m rv64m rv128m +|div | rd rs1 rs2 | r rv32m rv64m rv128m +|divu | rd rs1 rs2 | r rv32m rv64m rv128m +|rem | rd rs1 rs2 | r rv32m rv64m rv128m +|remu | rd rs1 rs2 | r rv32m rv64m rv128m # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|mulw | rd rs1 rs2 31..25=1 r rv64m rv128m -|divw | rd rs1 rs2 31..25=1 r rv64m rv128m -|divuw | rd rs1 rs2 31..25=1 r rv64m rv128m -|remw | rd rs1 rs2 31..25=1 r rv64m rv128m -|remuw | rd rs1 rs2 31..25=1 r rv64m rv128m +|mulw | rd rs1 rs2 | r rv64m rv128m +|divw | rd rs1 rs2 | r rv64m rv128m +|divuw | rd rs1 rs2 | r rv64m rv128m +|remw | rd rs1 rs2 | r rv64m rv128m +|remuw | rd rs1 rs2 | r rv64m rv128m # RV128M "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|muld | rd rs1 rs2 31..25=1 r rv128m -|divd | rd rs1 rs2 31..25=1 r rv128m -|divud | rd rs1 rs2 31..25=1 r rv128m -|remd | rd rs1 rs2 31..25=1 r rv128m -|remud | rd rs1 rs2 31..25=1 r rv128m +|muld | rd rs1 rs2 | r rv128m +|divd | rd rs1 rs2 | r rv128m +|divud | rd rs1 rs2 | r rv128m +|remd | rd rs1 rs2 | r rv128m +|remud | rd rs1 rs2 | r rv128m # RV32A "RV32A Standard Extension for Atomic Instructions" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|lr.w | rd rs1 24..20=0 aq rl 31...2=0x0B 1..0=3 r·l rv32a rv64a rv128a -|sc.w | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amoswap.w| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amoadd.w | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amoxor.w | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amoor.w | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amoand.w | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amomin.w | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amomax.w | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amominu.w| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a -|amomaxu.w| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv32a rv64a rv128a +|lr.w | rd rs1 | r·l rv32a rv64a rv128a +|sc.w | rd rs1 rs2 | r·a rv32a rv64a rv128a +|amoswap.w| rd rs1 rs2 | r·a rv32a rv64a rv128a +|amoadd.w | rd rs1 rs2 | r·a rv32a rv64a rv128a +|amoxor.w | rd rs1 rs2 | r·a rv32a rv64a rv128a +|amoor.w | rd rs1 rs2 | r·a rv32a rv64a rv128a +|amoand.w | rd rs1 rs2 | r·a rv32a rv64a rv128a +|amomin.w | rd rs1 rs2 | r·a rv32a rv64a rv128a +|amomax.w | rd rs1 rs2 | r·a rv32a rv64a rv128a +|amominu.w| rd rs1 rs2 | r·a rv32a rv64a rv128a +|amomaxu.w| rd rs1 rs2 | r·a rv32a rv64a rv128a # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|lr.d | rd rs1 24..20=0 aq rl 31...2=0x0B 1..0=3 r·l rv64a rv128a -|sc.d | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amoswap.d| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amoadd.d | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amoxor.d | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amoor.d | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amoand.d | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amomin.d | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amomax.d | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amominu.d| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a -|amomaxu.d| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv64a rv128a +|lr.d | rd rs1 | r·l rv64a rv128a +|sc.d | rd rs1 rs2 | r·a rv64a rv128a +|amoswap.d| rd rs1 rs2 | r·a rv64a rv128a +|amoadd.d | rd rs1 rs2 | r·a rv64a rv128a +|amoxor.d | rd rs1 rs2 | r·a rv64a rv128a +|amoor.d | rd rs1 rs2 | r·a rv64a rv128a +|amoand.d | rd rs1 rs2 | r·a rv64a rv128a +|amomin.d | rd rs1 rs2 | r·a rv64a rv128a +|amomax.d | rd rs1 rs2 | r·a rv64a rv128a +|amominu.d| rd rs1 rs2 | r·a rv64a rv128a +|amomaxu.d| rd rs1 rs2 | r·a rv64a rv128a # RV128A "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|lr.q | rd rs1 24..20=0 aq rl 31...2=0x0B 1..0=3 r·l rv128a -|sc.q | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amoswap.q| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amoadd.q | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amoxor.q | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amoor.q | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amoand.q | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amomin.q | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amomax.q | rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amominu.q| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a -|amomaxu.q| rd rs1 rs2 aq rl 31...2=0x0B 1..0=3 r·a rv128a +|lr.q | rd rs1 | r·l rv128a +|sc.q | rd rs1 rs2 | r·a rv128a +|amoswap.q| rd rs1 rs2 | r·a rv128a +|amoadd.q | rd rs1 rs2 | r·a rv128a +|amoxor.q | rd rs1 rs2 | r·a rv128a +|amoor.q | rd rs1 rs2 | r·a rv128a +|amoand.q | rd rs1 rs2 | r·a rv128a +|amomin.q | rd rs1 rs2 | r·a rv128a +|amomax.q | rd rs1 rs2 | r·a rv128a +|amominu.q| rd rs1 rs2 | r·a rv128a +|amomaxu.q| rd rs1 rs2 | r·a rv128a # RV32S "RV32S Standard Extension for Supervisor-level Instructions" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|ecall | 11..7=0 19..15=0 31..20=0x000 none rv32s rv64s rv128s -|ebreak | 11..7=0 19..15=0 31..20=0x001 none rv32s rv64s rv128s -|uret | 11..7=0 19..15=0 31..20=0x002 none rv32s rv64s rv128s -|sret | 11..7=0 19..15=0 31..20=0x102 none rv32s rv64s rv128s -|hret | 11..7=0 19..15=0 31..20=0x202 none rv32s rv64s rv128s -|mret | 11..7=0 19..15=0 31..20=0x302 none rv32s rv64s rv128s -|dret | 11..7=0 19..15=0 31..20=0x7b2 none rv32s rv64s rv128s -|sfence.vm 11..7=0 rs1 31..20=0x104 r+sf rv32s rv64s rv128s -|sfence.vma|11..7=0 rs1 rs2 31..25=0x009 r+sfa rv32s rv64s rv128s -|wfi | 11..7=0 19..15=0 31..20=0x105 none rv32s rv64s rv128s -|csrrw | rd rs1 csr12 i·csr rv32s rv64s rv128s -|csrrs | rd rs1 csr12 i·csr rv32s rv64s rv128s -|csrrc | rd rs1 csr12 i·csr rv32s rv64s rv128s -|csrrwi | rd zimm csr12 i·csr+i rv32s rv64s rv128s -|csrrsi | rd zimm csr12 i·csr+i rv32s rv64s rv128s -|csrrci | rd zimm csr12 i·csr+i rv32s rv64s rv128s +|ecall | | none rv32s rv64s rv128s +|ebreak | | none rv32s rv64s rv128s +|uret | | none rv32s rv64s rv128s +|sret | | none rv32s rv64s rv128s +|hret | | none rv32s rv64s rv128s +|mret | | none rv32s rv64s rv128s +|dret | | none rv32s rv64s rv128s +|sfence.vm| rs1 | r+sf rv32s rv64s rv128s +|sfence.vma| rs1 rs2 | r+sfa rv32s rv64s rv128s +|wfi | | none rv32s rv64s rv128s +|csrrw | rd rs1 csr12 | i·csr rv32s rv64s rv128s +|csrrs | rd rs1 csr12 | i·csr rv32s rv64s rv128s +|csrrc | rd rs1 csr12 | i·csr rv32s rv64s rv128s +|csrrwi | rd zimm csr12 | i·csr+i rv32s rv64s rv128s +|csrrsi | rd zimm csr12 | i·csr+i rv32s rv64s rv128s +|csrrci | rd zimm csr12 | i·csr+i rv32s rv64s rv128s # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|flw | frd rs1 oimm12 14..1.0=3 i+lf rv32f rv64f rv128f -|fsw | rs1 frs2 simm12 14..1.0=3 s+f rv32f rv64f rv128f -|fmadd.s | frd frs1 frs2 frs3 rm .0=3 r4·m rv32f rv64f rv128f -|fmsub.s | frd frs1 frs2 frs3 rm .0=3 r4·m rv32f rv64f rv128f -|fnmsub.s | frd frs1 frs2 frs3 rm .0=3 r4·m rv32f rv64f rv128f -|fnmadd.s | frd frs1 frs2 frs3 rm .0=3 r4·m rv32f rv64f rv128f -|fadd.s | frd frs1 frs2 31..27=0x00 rm .0=3 r·m+3f rv32f rv64f rv128f -|fsub.s | frd frs1 frs2 31..27=0x01 rm .0=3 r·m+3f rv32f rv64f rv128f -|fmul.s | frd frs1 frs2 31..27=0x02 rm .0=3 r·m+3f rv32f rv64f rv128f -|fdiv.s | frd frs1 frs2 31..27=0x03 rm .0=3 r·m+3f rv32f rv64f rv128f -|fsgnj.s | frd frs1 frs2 31..27=0x04 14..1.0=3 r+3f rv32f rv64f rv128f -|fsgnjn.s | frd frs1 frs2 31..27=0x04 14..1.0=3 r+3f rv32f rv64f rv128f -|fsgnjx.s | frd frs1 frs2 31..27=0x04 14..1.0=3 r+3f rv32f rv64f rv128f -|fmin.s | frd frs1 frs2 31..27=0x05 14..1.0=3 r+3f rv32f rv64f rv128f -|fmax.s | frd frs1 frs2 31..27=0x05 14..1.0=3 r+3f rv32f rv64f rv128f -|fsqrt.s | frd frs1 24..20=0 31..27=0x0B rm .0=3 r·m+ff rv32f rv64f rv128f -|fle.s | rd frs1 frs2 31..27=0x14 14..1.0=3 r+rff rv32f rv64f rv128f -|flt.s | rd frs1 frs2 31..27=0x14 14..1.0=3 r+rff rv32f rv64f rv128f -|feq.s | rd frs1 frs2 31..27=0x14 14..1.0=3 r+rff rv32f rv64f rv128f -|fcvt.w.s | rd frs1 24..20=0 31..27=0x18 rm .0=3 r·m+rf rv32f rv64f rv128f -|fcvt.wu.s| rd frs1 24..20=1 31..27=0x18 rm .0=3 r·m+rf rv32f rv64f rv128f -|fcvt.s.w | frd rs1 24..20=0 31..27=0x1A rm .0=3 r·m+fr rv32f rv64f rv128f -|fcvt.s.wu| frd rs1 24..20=1 31..27=0x1A rm .0=3 r·m+fr rv32f rv64f rv128f -|fmv.x.s | rd frs1 24..20=0 31..27=0x1C 14..1.0=3 r+rf rv32f rv64f rv128f -|fclass.s | rd frs1 24..20=0 31..27=0x1C 14..1.0=3 r+rf rv32f rv64f rv128f -|fmv.s.x | frd rs1 24..20=0 31..27=0x1E 14..1.0=3 r+fr rv32f rv64f rv128f +|flw | frd rs1 oimm12 | i+lf rv32f rv64f rv128f +|fsw | rs1 frs2 simm12 | s+f rv32f rv64f rv128f +|fmadd.s | frd frs1 frs2 frs3 rm | r4·m rv32f rv64f rv128f +|fmsub.s | frd frs1 frs2 frs3 rm | r4·m rv32f rv64f rv128f +|fnmsub.s | frd frs1 frs2 frs3 rm | r4·m rv32f rv64f rv128f +|fnmadd.s | frd frs1 frs2 frs3 rm | r4·m rv32f rv64f rv128f +|fadd.s | frd frs1 frs2 rm | r·m+3f rv32f rv64f rv128f +|fsub.s | frd frs1 frs2 rm | r·m+3f rv32f rv64f rv128f +|fmul.s | frd frs1 frs2 rm | r·m+3f rv32f rv64f rv128f +|fdiv.s | frd frs1 frs2 rm | r·m+3f rv32f rv64f rv128f +|fsgnj.s | frd frs1 frs2 | r+3f rv32f rv64f rv128f +|fsgnjn.s | frd frs1 frs2 | r+3f rv32f rv64f rv128f +|fsgnjx.s | frd frs1 frs2 | r+3f rv32f rv64f rv128f +|fmin.s | frd frs1 frs2 | r+3f rv32f rv64f rv128f +|fmax.s | frd frs1 frs2 | r+3f rv32f rv64f rv128f +|fsqrt.s | frd frs1 rm | r·m+ff rv32f rv64f rv128f +|fle.s | rd frs1 frs2 | r+rff rv32f rv64f rv128f +|flt.s | rd frs1 frs2 | r+rff rv32f rv64f rv128f +|feq.s | rd frs1 frs2 | r+rff rv32f rv64f rv128f +|fcvt.w.s | rd frs1 rm | r·m+rf rv32f rv64f rv128f +|fcvt.wu.s| rd frs1 rm | r·m+rf rv32f rv64f rv128f +|fcvt.s.w | frd rs1 rm | r·m+fr rv32f rv64f rv128f +|fcvt.s.wu| frd rs1 rm | r·m+fr rv32f rv64f rv128f +|fmv.x.s | rd frs1 | r+rf rv32f rv64f rv128f +|fclass.s | rd frs1 | r+rf rv32f rv64f rv128f +|fmv.s.x | frd rs1 | r+fr rv32f rv64f rv128f # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" | (23..18) | (17..12) | (11..6) | (5...0) | | -------- | -------- | ------- | ------- | -|fcvt.l.s | rd frs1 24..20=2 31..27=0x18 rm r·m+rf rv64f rv128f -|fcvt.lu.s| rd frs1 24..20=3 31..27=0x18 rm r·m+rf rv64f rv128f -|fcvt.s.l | frd rs1 24..20=2 31..27=0x1A rm r·m+fr rv64f rv128f -|fcvt.s.lu| frd rs1 24..20=3 31..27=0x1A rm r·m+fr rv64f rv128f +|fcvt.l.s | rd frs1 rm | r·m+rf rv64f rv128f +|fcvt.lu.s| rd frs1 rm | r·m+rf rv64f rv128f +|fcvt.s.l | frd rs1 rm | r·m+fr rv64f rv128f +|fcvt.s.lu| frd rs1 rm | r·m+fr rv64f rv128f # RV32D "RV32D Standard Extension for Double-Precision Floating-Point"