From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 17 Oct 2006 22:50:19 +0000 (-0400)
Subject: Fixes for uni-coherence in timing mode for FS.
X-Git-Tag: m5_2.0_beta2~83^2~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c582c7e144aef0bfc9d14bb4690d56d1688496a;p=gem5.git

Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
    Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
    Only deallocate once

--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
---

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 07d4ebb42..54b652813 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -80,7 +80,10 @@ template<class Impl>
 bool
 DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
 {
-    fetch->processCacheCompletion(pkt);
+    if (pkt->isResponse()) {
+        fetch->processCacheCompletion(pkt);
+    }
+    //else Snooped a coherence request, just return
     return true;
 }
 
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 7b7d1eb8e..337ee0372 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -63,7 +63,14 @@ template <class Impl>
 bool
 LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
 {
-    lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+    if (pkt->isResponse()) {
+        lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+    }
+    else {
+    //else it is a coherence request, maybe you need to do something
+        warn("Recieved a coherence request (Invalidate??), 03CPU doesn't"
+             "update LSQ for these\n");
+    }
     return true;
 }
 
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index fe421ae6c..acda254c3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -101,7 +101,7 @@ AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
 Tick
 AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
 {
-    panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
+    //Snooping a coherence request, just return
     return curTick;
 }
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ad5c0e5d6..0cc10ae94 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -528,17 +528,23 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    // delay processing of returned data until next CPU clock edge
-    Tick time = pkt->req->getTime();
-    while (time < curTick)
-        time += lat;
-
-    if (time == curTick)
-        cpu->completeIfetch(pkt);
-    else
-        tickEvent.schedule(pkt, time);
-
-    return true;
+    if (pkt->isResponse()) {
+        // delay processing of returned data until next CPU clock edge
+        Tick time = pkt->req->getTime();
+        while (time < curTick)
+            time += lat;
+
+        if (time == curTick)
+            cpu->completeIfetch(pkt);
+        else
+            tickEvent.schedule(pkt, time);
+
+        return true;
+    }
+    else {
+        //Snooping a Coherence Request, do nothing
+        return true;
+    }
 }
 
 void
@@ -600,17 +606,23 @@ TimingSimpleCPU::completeDrain()
 bool
 TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
 {
-    // delay processing of returned data until next CPU clock edge
-    Tick time = pkt->req->getTime();
-    while (time < curTick)
-        time += lat;
+    if (pkt->isResponse()) {
+        // delay processing of returned data until next CPU clock edge
+        Tick time = pkt->req->getTime();
+        while (time < curTick)
+            time += lat;
 
-    if (time == curTick)
-        cpu->completeDataAccess(pkt);
-    else
-        tickEvent.schedule(pkt, time);
+        if (time == curTick)
+            cpu->completeDataAccess(pkt);
+        else
+            tickEvent.schedule(pkt, time);
 
-    return true;
+        return true;
+    }
+    else {
+        //Snooping a coherence req, do nothing
+        return true;
+    }
 }
 
 void
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 6250b72d4..ebcf83b92 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -331,7 +331,7 @@ BaseCache::CacheEvent::process()
             pkt = cachePort->cache->getCoherencePacket();
             MSHR* cshr = (MSHR*) pkt->senderState;
             bool success = cachePort->sendTiming(pkt);
-            cachePort->cache->sendResult(pkt, cshr, success);
+            cachePort->cache->sendCoherenceResult(pkt, cshr, success);
             cachePort->waitingOnRetry = !success;
             if (cachePort->waitingOnRetry)
                 DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 751de4801..464266a29 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -53,11 +53,11 @@ UniCoherence::sendResult(Packet * &pkt, MSHR* cshr, bool success)
     if (success)
     {
         bool unblock = cshrs.isFull();
-        cshrs.markInService(cshr);
+//        cshrs.markInService(cshr);
+        cshrs.deallocate(cshr);
         if (!cshrs.havePending()) {
             cache->clearSlaveRequest(Request_Coherence);
         }
-        cshrs.deallocate(cshr);
         if (unblock) {
             //since CSHRs are always used as buffers, should always get rid of one
             assert(!cshrs.isFull());