From: whitequark <whitequark@whitequark.org>
Date: Tue, 14 Apr 2020 12:12:50 +0000 (+0000)
Subject: write_verilog: fix precondition check.
X-Git-Tag: working-ls180~659^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c64d37a4c3279ca037d4eae79f6ea60ca582457;p=yosys.git

write_verilog: fix precondition check.
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 5467e250b..11b2ae10f 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1984,7 +1984,7 @@ struct VerilogBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 		if (extmem)
 		{
-			if (filename.empty())
+			if (filename == "<stdout>")
 				log_cmd_error("Option -extmem must be used with a filename.\n");
 			extmem_prefix = filename.substr(0, filename.rfind('.'));
 		}