From: Vegard Storheil Eriksen Date: Mon, 15 Jun 2020 14:08:49 +0000 (+0200) Subject: bios/linker: Place .data in sram with initial copy in rom. X-Git-Tag: 24jan2021_ls180~177^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c68d715032c1e5bdd2f52d8523beac484581556;p=litex.git bios/linker: Place .data in sram with initial copy in rom. --- diff --git a/litex/soc/cores/cpu/blackparrot/crt0.S b/litex/soc/cores/cpu/blackparrot/crt0.S index 2b82399d..5f5cb096 100644 --- a/litex/soc/cores/cpu/blackparrot/crt0.S +++ b/litex/soc/cores/cpu/blackparrot/crt0.S @@ -57,6 +57,19 @@ crt_init: la a0, trap_entry csrw mtvec, a0 +data_init: + la a0, _fdata + la a1, _edata + la a2, _fdata_rom +data_loop: + beq a0,a1,data_done + ld a3,0(a2) + sd a3,0(a0) + add a0,a0,8 + add a2,a2,8 + j data_loop +data_done: + bss_init: la a0, _fbss la a1, _ebss diff --git a/litex/soc/cores/cpu/cv32e40p/crt0.S b/litex/soc/cores/cpu/cv32e40p/crt0.S index 30b372ab..d654998b 100644 --- a/litex/soc/cores/cpu/cv32e40p/crt0.S +++ b/litex/soc/cores/cpu/cv32e40p/crt0.S @@ -94,6 +94,19 @@ crt_init: la a0, vector_table csrw mtvec, a0 +data_init: + la a0, _fdata + la a1, _edata + la a2, _fdata_rom +data_loop: + beq a0,a1,data_done + lw a3,0(a2) + sw a3,0(a0) + add a0,a0,4 + add a2,a2,4 + j data_loop +data_done: + bss_init: la a0, _fbss la a1, _ebss diff --git a/litex/soc/cores/cpu/lm32/crt0.S b/litex/soc/cores/cpu/lm32/crt0.S index 50319e8c..85303ba3 100644 --- a/litex/soc/cores/cpu/lm32/crt0.S +++ b/litex/soc/cores/cpu/lm32/crt0.S @@ -112,10 +112,9 @@ _crt0: mvhi sp, hi(_fstack) ori sp, sp, lo(_fstack) -#ifdef EXECUTE_IN_PLACE /* Load DATA */ - mvhi r1, hi(_erodata) - ori r1, r1, lo(_erodata) + mvhi r1, hi(_fdata_rom) + ori r1, r1, lo(_fdata_rom) mvhi r2, hi(_fdata) ori r2, r2, lo(_fdata) mvhi r3, hi(_edata) @@ -128,7 +127,6 @@ _crt0: addi r1, r1, 4 addi r2, r2, 4 bi .moveDATA -#endif .doBSS: /* Clear BSS */ diff --git a/litex/soc/cores/cpu/minerva/crt0.S b/litex/soc/cores/cpu/minerva/crt0.S index 6f6e9e6c..f01e5176 100644 --- a/litex/soc/cores/cpu/minerva/crt0.S +++ b/litex/soc/cores/cpu/minerva/crt0.S @@ -9,14 +9,26 @@ reset_vector: la t0, trap_vector csrw mtvec, t0 + // initialize .data + la t0, _fdata + la t1, _edata + la t2, _fdata_rom +1: beq t0, t1, 2f + lw t3, 0(t0) + sw t3, 0(t2) + addi t0, t0, 4 + addi t2, t2, 4 + j 1b +2: + // initialize .bss la t0, _fbss la t1, _ebss -1: beq t0, t1, 2f +1: beq t0, t1, 3f sw zero, 0(t0) addi t0, t0, 4 j 1b -2: +3: // enable external interrupts li t0, MIE_MEIE csrs mie, t0 diff --git a/litex/soc/cores/cpu/picorv32/crt0.S b/litex/soc/cores/cpu/picorv32/crt0.S index 49883ed0..3307eba3 100644 --- a/litex/soc/cores/cpu/picorv32/crt0.S +++ b/litex/soc/cores/cpu/picorv32/crt0.S @@ -194,9 +194,8 @@ _crt0: la t1, _irq_mask sw t0, 0(t1) -#ifdef EXECUTE_IN_PLACE /* Load DATA */ - la t0, _erodata + la t0, _fdata_rom la t1, _fdata la t2, _edata 3: @@ -206,7 +205,6 @@ _crt0: addi t0, t0, 4 addi t1, t1, 4 bltu t1, t2, 3b -#endif /* Clear BSS */ la t0, _fbss diff --git a/litex/soc/cores/cpu/rocket/crt0.S b/litex/soc/cores/cpu/rocket/crt0.S index 69b9d574..8a9514d5 100644 --- a/litex/soc/cores/cpu/rocket/crt0.S +++ b/litex/soc/cores/cpu/rocket/crt0.S @@ -57,6 +57,19 @@ crt_init: la a0, trap_entry csrw mtvec, a0 +data_init: + la a0, _fdata + la a1, _edata + la a2, _fdata_rom +data_loop: + beq a0,a1,data_done + ld a3,0(a2) + sd a3,0(a0) + add a0,a0,8 + add a2,a2,8 + j data_loop +data_done: + bss_init: la a0, _fbss la a1, _ebss diff --git a/litex/soc/cores/cpu/serv/crt0.S b/litex/soc/cores/cpu/serv/crt0.S index 6f6e9e6c..f01e5176 100644 --- a/litex/soc/cores/cpu/serv/crt0.S +++ b/litex/soc/cores/cpu/serv/crt0.S @@ -9,14 +9,26 @@ reset_vector: la t0, trap_vector csrw mtvec, t0 + // initialize .data + la t0, _fdata + la t1, _edata + la t2, _fdata_rom +1: beq t0, t1, 2f + lw t3, 0(t0) + sw t3, 0(t2) + addi t0, t0, 4 + addi t2, t2, 4 + j 1b +2: + // initialize .bss la t0, _fbss la t1, _ebss -1: beq t0, t1, 2f +1: beq t0, t1, 3f sw zero, 0(t0) addi t0, t0, 4 j 1b -2: +3: // enable external interrupts li t0, MIE_MEIE csrs mie, t0 diff --git a/litex/soc/cores/cpu/vexriscv/crt0.S b/litex/soc/cores/cpu/vexriscv/crt0.S index c27a3da7..90beab95 100644 --- a/litex/soc/cores/cpu/vexriscv/crt0.S +++ b/litex/soc/cores/cpu/vexriscv/crt0.S @@ -58,6 +58,19 @@ crt_init: la a0, trap_entry csrw mtvec, a0 +data_init: + la a0, _fdata + la a1, _edata + la a2, _fdata_rom +data_loop: + beq a0,a1,data_done + lw a3,0(a2) + sw a3,0(a0) + add a0,a0,4 + add a2,a2,4 + j data_loop +data_done: + bss_init: la a0, _fbss la a1, _ebss diff --git a/litex/soc/software/bios/helpers.c b/litex/soc/software/bios/helpers.c index 535dd61b..fad46419 100644 --- a/litex/soc/software/bios/helpers.c +++ b/litex/soc/software/bios/helpers.c @@ -11,7 +11,7 @@ #include "helpers.h" #include "command.h" -extern unsigned int _ftext, _edata; +extern unsigned int _ftext, _edata_rom; #define NUMBER_OF_BYTES_ON_A_LINE 16 void dump_bytes(unsigned int *ptr, int count, unsigned long addr) @@ -59,14 +59,14 @@ void crcbios(void) unsigned int actual_crc; /* - * _edata is located right after the end of the flat + * _edata_rom is located right after the end of the flat * binary image. The CRC tool writes the 32-bit CRC here. - * We also use the address of _edata to know the length + * We also use the address of _edata_rom to know the length * of our code. */ offset_bios = (unsigned long)&_ftext; - expected_crc = _edata; - length = (unsigned long)&_edata - offset_bios; + expected_crc = _edata_rom; + length = (unsigned long)&_edata_rom - offset_bios; actual_crc = crc32((unsigned char *)offset_bios, length); if (expected_crc == actual_crc) printf(" BIOS CRC passed (%08x)\n", actual_crc); diff --git a/litex/soc/software/bios/linker.ld b/litex/soc/software/bios/linker.ld index a29eb490..07021253 100644 --- a/litex/soc/software/bios/linker.ld +++ b/litex/soc/software/bios/linker.ld @@ -53,7 +53,7 @@ SECTIONS FILL(0); . = ALIGN(8); _edata = .; - } > rom + } > sram AT > rom .bss : { @@ -78,3 +78,6 @@ SECTIONS } PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 8); + +PROVIDE(_fdata_rom = LOADADDR(.data)); +PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));