From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 8 Jun 2021 16:33:16 +0000 (+0100)
Subject: whoops, carry-over during rounding picks MSB not LSB
X-Git-Tag: xlen-bcd~477
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c7dcdb4586a36975b002f87f65f35cfe43b5e3c;p=openpower-isa.git

whoops, carry-over during rounding picks MSB not LSB
---

diff --git a/openpower/isafunctions/double2single.mdwn b/openpower/isafunctions/double2single.mdwn
index bda22763..31686e4d 100644
--- a/openpower/isafunctions/double2single.mdwn
+++ b/openpower/isafunctions/double2single.mdwn
@@ -29,7 +29,7 @@ Round to Single-Precision instruction.
         tmp        <- [0]*25
         tmp[1:24]  <- frac[0:23]
         tmp[0:24]  <- tmp[0:24] + inc
-        carry_out  <- tmp[24]
+        carry_out  <- tmp[0]
         frac[0:23] <- tmp[1:24]
         if carry_out = 1 then
             exp[0:10] <- exp + 1
diff --git a/openpower/isafunctions/fpfromint.mdwn b/openpower/isafunctions/fpfromint.mdwn
index 2068509b..67ae7583 100644
--- a/openpower/isafunctions/fpfromint.mdwn
+++ b/openpower/isafunctions/fpfromint.mdwn
@@ -36,13 +36,13 @@ Convert From Integer instructions.
             tmp        <- [0]*25
             tmp[1:24]  <- frac[0:23]
             tmp[0:24]  <- tmp[0:24] + inc
-            carry_out  <- tmp[24]
+            carry_out  <- tmp[0]
             frac[0:23] <- tmp[1:24]
         else # tgt_precision = 'double-precision'
             tmp        <- [0]*54
             tmp[1:53]  <- frac[0:52]
             tmp[0:53]  <- tmp[0:53] + inc
-            carry_out  <- tmp[53]
+            carry_out  <- tmp[0]
             frac[0:52] <- tmp[1:53]
         if carry_out = 1 then exp <- exp + 1
         # TODO, later
diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 83812637..bdb9351e 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -257,6 +257,21 @@ class DecoderTestCase(FHDLTestCase):
             # result should be -ve zero not +ve zero
             self.assertEqual(sim.fpr(3), SelectableInt(0x8000000000000000, 64))
 
+    def test_fp_muls5(self):
+        """>>> lst = ["fmuls 3, 1, 2",
+                     ]
+        """
+        lst = ["fmuls 3, 1, 2", #
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0xbfb0ab5100000000
+        fprs[2] = 0xbdca000000000000
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(3), SelectableInt(0x3d8b1663a0000000, 64))
+
     def test_fp_mul(self):
         """>>> lst = ["fmul 3, 1, 2",
                      ]