From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 10 Jul 2019 14:50:06 +0000 (+0200)
Subject: soc_zynq: move axi gp0 clock connection to add_gp0 method
X-Git-Tag: 24jan2021_ls180~1111
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c8c03710810bdf777e85156826758a96a1afe46;p=litex.git

soc_zynq: move axi gp0 clock connection to add_gp0 method
---

diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py
index 26aa4457..0c237a65 100644
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@@ -72,9 +72,6 @@ class SoCZynq(SoCCore):
 
             # fabric clk
             o_FCLK_CLK0=ClockSignal("sys"),
-
-            # axi gp0 clk
-            i_M_AXI_GP0_ACLK=ClockSignal("sys"),
         )
         platform.add_ip(os.path.join("ip", ps7_name + ".xci"))
 
@@ -83,6 +80,9 @@ class SoCZynq(SoCCore):
     def add_gp0(self):
         self.axi_gp0 = axi_gp0 = axi.AXIInterface(data_width=32, address_width=32, id_width=12)
         self.ps7_params.update(
+            # axi gp0 clk
+            i_M_AXI_GP0_ACLK=ClockSignal("sys"),
+
             # axi gp0 aw
             o_M_AXI_GP0_AWVALID=axi_gp0.aw.valid,
             i_M_AXI_GP0_AWREADY=axi_gp0.aw.ready,