From: lkcl <lkcl@web>
Date: Wed, 22 Jun 2022 10:24:05 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1608
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c8ee475047773d049beb3a18c5a3cc2a684dff6;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index cd6d492ef..c337395c4 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -12,7 +12,7 @@ Links:
  out of scope for this document [[openpower/sv/3d_vector_ops]]
 * [[simple_v_extension/specification/bitmanip]] previous version,
   contains pseudocode for sof, sif, sbf
-* https://en.m.wikipedia.org/wiki/X86_Bit_manipulation_instruction_set#TBM_(Trailing_Bit_Manipulation)
+* <https://en.m.wikipedia.org/wiki/X86_Bit_manipulation_instruction_set#TBM_(Trailing_Bit_Manipulation)>
 
 The core Power ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism.
 Therefore there are not that many cases where *actual* Vector