From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Fri, 9 Apr 2021 20:50:05 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1077^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9c9a0a0d42cb752c94fa4e0a8b34ff21c017cf19;p=libreriscv.git

---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index aad393606..8bd65546a 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -223,10 +223,12 @@ and therefore have no value are marked with 'NOT'
 
 Image of JTAG jumper wire connections on ULX3S FPGA side
 
-[[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="200x" ]] 
+[[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]] 
 
 Image of JTAG jumper wire connections on ft232r side
 
+[[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]] 
+
 # VERSA ECP5 Connections
 
 Table of connections: