From: lkcl Date: Mon, 16 Nov 2020 08:14:00 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1784 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9caf380f0daf409c6be125886c6a744b3f521dfa;p=libreriscv.git --- diff --git a/openpower/sv/major_opcode_allocation.mdwn b/openpower/sv/major_opcode_allocation.mdwn index 3f15c180f..048bd3f13 100644 --- a/openpower/sv/major_opcode_allocation.mdwn +++ b/openpower/sv/major_opcode_allocation.mdwn @@ -24,7 +24,18 @@ opportunity to switch into "16 bit mode". Interestingly SV-C32 could likewise switch into the same. VBLOCK can be added later by using further VSX dedicated major opcodes -(EXT62, EXT63) +(EXT62, EXT60) + +* EXT01 - v3.1B prefix +* EXT04 - vector/bcd +* EXT06 - vector +* EXT57 - vector ld +* EXT58 - ld (leave ok) +* EXT59 - FP (leave ok) +* EXT60 - vector +* EXT61 - st (leave ok) +* EXT62 - vector st +* EXT63 - FP (leave ok) # LE/BE complications.