From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 20:09:30 +0000 (+0100)
Subject: add a DIVS function as separate and discrete from floor_div
X-Git-Tag: div_pipeline~100
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9cde3002d533352fdf8ed464fa46d4acd548b051;p=soc.git

add a DIVS function as separate and discrete from floor_div
likewise for MODS and MULS
---

diff --git a/libreriscv b/libreriscv
index 2e8b6bf4..4aa6408d 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 2e8b6bf44d7519bfd2085023649f7e5b9acd3b6f
+Subproject commit 4aa6408d7d1bfc0246020fa69b0f5f850f8e8e70
diff --git a/src/soc/decoder/helpers.py b/src/soc/decoder/helpers.py
index 8cab8d50..40ddb088 100644
--- a/src/soc/decoder/helpers.py
+++ b/src/soc/decoder/helpers.py
@@ -1,9 +1,15 @@
 import unittest
 from soc.decoder.selectable_int import SelectableInt, onebit
-from nmutil.divmod import trunc_div, trunc_rem
+from nmutil.divmod import trunc_divs, trunc_rems
+from operator import floordiv, mod
 from soc.decoder.selectable_int import selectltu as ltu
 from soc.decoder.selectable_int import selectgtu as gtu
 
+trunc_div = floordiv
+trunc_rem = mod
+DIVS = trunc_divs
+MODS = trunc_rems
+
 """
 Links:
 * https://bugs.libre-soc.org/show_bug.cgi?id=324 - add trunc_div and trunc_rem
diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 711c9650..ef6e46dd 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -15,7 +15,7 @@ from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
                                      insns, InternalOp)
-from soc.decoder.helpers import exts, trunc_div, trunc_rem
+from soc.decoder.helpers import exts
 from soc.consts import PI, MSR
 
 from collections import namedtuple
diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 61d6860d..f06d996f 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -21,7 +21,7 @@ header = """\
 from soc.decoder.isa.caller import inject, instruction_info
 from soc.decoder.helpers import (EXTS, EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
                                  ne, eq, gt, ge, lt, le, ltu, gtu, length,
-                                 trunc_div, trunc_rem)
+                                 trunc_divs, trunc_rems, MULS, DIVS, MODS)
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.selectable_int import selectconcat as concat
 from soc.decoder.orderedset import OrderedSet
diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index ba153112..02f9f996 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -17,6 +17,9 @@ from soc.fu.div.pipeline import DIVBasePipe
 from soc.fu.div.pipe_data import DIVPipeSpec
 import random
 
+def log_rand(n, min_val=1):
+    logrange = random.randint(1, n)
+    return random.randint(min_val, (1<<logrange)-1)
 
 def get_cu_inputs(dec2, sim):
     """naming (res) must conform to DIVFunctionUnit input regspec
@@ -167,18 +170,32 @@ class DIVTestCase(FHDLTestCase):
             choice = random.choice(insns)
             lst = [f"{choice} 3, 1, 2"]
             initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<64)-1)
-            initial_regs[2] = random.randint(0, (1<<64)-1)
+            initial_regs[1] = log_rand(32)
+            initial_regs[2] = log_rand(32)
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_divwuo_regression_1(self):
+        lst = ["divwuo. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x7591a398c4e32b68
+        initial_regs[2] = 0x48674ab432867d69
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_divwuo_1(self):
+        lst = ["divwuo. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x50
+        initial_regs[2] = 0x2
+        self.run_tst_program(Program(lst), initial_regs)
+
     def test_rand_divwu(self):
         insns = ["divwu", "divwu.", "divwuo", "divwuo."]
         for i in range(40):
             choice = random.choice(insns)
             lst = [f"{choice} 3, 1, 2"]
             initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<64)-1)
-            initial_regs[2] = random.randint(0, (1<<64)-1)
+            initial_regs[1] = log_rand(32)
+            initial_regs[2] = log_rand(32)
             self.run_tst_program(Program(lst), initial_regs)
 
     def test_ilang(self):