From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Jul 2020 13:11:47 +0000 (+0100)
Subject: adding OP_MTMSR test
X-Git-Tag: div_pipeline~162^2~34
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9cf108511e2b419efe081018e940fa3940d746f7;p=soc.git

adding OP_MTMSR test
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 8c68e7fc..0ddb2823 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -164,11 +164,14 @@ class TrapMainStage(PipeModBase):
                         comb += srr1_o.data[PI.ILLEG].eq(1)
 
             # move to MSR
-            with m.Case(InternalOp.OP_MTMSRD):
+            with m.Case(InternalOp.OP_MTMSRD, InternalOp.OP_MTMSR):
                 L = self.fields.FormX.L[0:-1] # X-Form field L
+                # start with copy of msr
+                comb += msr_o.eq(msr_i)
                 with m.If(L):
                     # just update RI..EE
-                    comb += msr_o.data[MSR.RI:MSR.EE].eq(a_i[MSR.RI:MSR.EE])
+                    comb += msr_o.data[MSR.RI].eq(a_i[MSR.RI])
+                    comb += msr_o.data[MSR.EE].eq(a_i[MSR.EE])
                 with m.Else():
                     # Architecture says to leave out bits 3 (HV), 51 (ME)
                     # and 63 (LE) (IBM bit numbering)