From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 26 Mar 2020 20:31:06 +0000 (+0000)
Subject: add TODO for cry_in==CA
X-Git-Tag: div_pipeline~1619
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d09af12cdf661cd8ddb24853be8d11f6439c0f7;p=soc.git

add TODO for cry_in==CA
---

diff --git a/src/soc/simulator/internalop_sim.py b/src/soc/simulator/internalop_sim.py
index 4afe531c..8f6a6421 100644
--- a/src/soc/simulator/internalop_sim.py
+++ b/src/soc/simulator/internalop_sim.py
@@ -134,7 +134,7 @@ class InternalOpSimulator:
         if cry_in == CryIn.ONE.value:
             carry = 1
         elif cry_in == CryIn.CA.value:
-            carry = TODO deliberately cause error here
+            carry = TODO # deliberately cause error here
 
         result = self.execute_alu_op(operand1, operand2, internal_op,
                                      carry=carry)