From: Gabe Black Date: Sat, 16 Dec 2006 16:35:40 +0000 (-0500) Subject: Merge zizzer:/bk/newmem X-Git-Tag: m5_2.0_beta3~274 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5;p=gem5.git Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/isa_parser.py: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/cpu/o3/iew_impl.hh: Hand Merge --HG-- extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47 --- 9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5 diff --cc src/arch/isa_parser.py index 59eb18c9c,aacdf455f..5f6a33565 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@@ -1307,7 -1362,7 +1362,7 @@@ class ControlRegOperand(Operand) bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') - base = 'xc->readMiscRegWithEffect(%s)' % self.reg_spec - base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx ++ base = 'xc->readMiscRegOperandWithEffect(%s)' % self.reg_spec if self.size == self.dflt_size: return '%s = %s;\n' % (self.base_name, base) else: diff --cc src/arch/sparc/intregfile.hh index d66d0fcb7,503f3c453..716d45a65 --- a/src/arch/sparc/intregfile.hh +++ b/src/arch/sparc/intregfile.hh @@@ -67,9 -72,10 +72,10 @@@ namespace SparcIS (unsigned int)(-1) : (1 << FrameOffsetBits) - 1; - IntReg regGlobals[MaxGL][RegsPerFrame]; + IntReg regGlobals[MaxGL+1][RegsPerFrame]; IntReg regSegments[2 * NWindows][RegsPerFrame]; IntReg microRegs[NumMicroIntRegs]; + IntReg regs[NumIntRegs]; enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames}; diff --cc src/arch/sparc/isa/formats/mem/basicmem.isa index 55e9fba45,d5b17d720..ed0c41e61 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@@ -52,13 -52,17 +52,17 @@@ def template MemDeclare { }}; let {{ - def doMemFormat(code, execute, faultCode, name, Name, opt_flags): + def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags): addrCalcReg = 'EA = Rs1 + Rs2;' addrCalcImm = 'EA = Rs1 + imm;' - iop = InstObjParams(name, Name, 'Mem', code, - opt_flags, {"fault_check": faultCode, "ea_code": addrCalcReg}) - iop_imm = InstObjParams(name, Name + "Imm", 'MemImm', code, - opt_flags, {"fault_check": faultCode, "ea_code": addrCalcImm}) + iop = InstObjParams(name, Name, 'Mem', + {"code": code, "fault_check": faultCode, + "ea_code": addrCalcReg}, + opt_flags) + iop_imm = InstObjParams(name, Name + "Imm", 'MemImm', + {"code": code, "fault_check": faultCode, + "ea_code": addrCalcImm}, + opt_flags) header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm) decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) decode_block = ROrImmDecode.subst(iop) @@@ -72,16 -76,16 +76,16 @@@ def format LoadAlt(code, asi, *opt_flag (header_output, decoder_output, exec_output, - decode_block) = doMemFormat(code, LoadExecute, + decode_block) = doMemFormat(code, LoadFuncs, - AlternateAsiPrivFaultCheck, name, Name, opt_flags) + AlternateASIPrivFaultCheck, name, Name, asi, opt_flags) }}; -def format StoreAlt(code, *opt_flags) {{ +def format StoreAlt(code, asi, *opt_flags) {{ (header_output, decoder_output, exec_output, - decode_block) = doMemFormat(code, StoreExecute, + decode_block) = doMemFormat(code, StoreFuncs, - AlternateAsiPrivFaultCheck, name, Name, opt_flags) + AlternateASIPrivFaultCheck, name, Name, asi, opt_flags) }}; def format Load(code, *opt_flags) {{ @@@ -89,7 -93,7 +93,7 @@@ decoder_output, exec_output, decode_block) = doMemFormat(code, - LoadExecute, '', name, Name, 0, opt_flags) - LoadFuncs, '', name, Name, opt_flags) ++ LoadFuncs, '', name, Name, 0, opt_flags) }}; def format Store(code, *opt_flags) {{ @@@ -97,5 -101,5 +101,5 @@@ decoder_output, exec_output, decode_block) = doMemFormat(code, - StoreExecute, '', name, Name, 0, opt_flags) - StoreFuncs, '', name, Name, opt_flags) ++ StoreFuncs, '', name, Name, 0, opt_flags) }}; diff --cc src/arch/sparc/isa/formats/mem/blockmem.isa index 7a1a58d13,c124dc600..a0b235a61 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@@ -314,26 -314,26 +314,26 @@@ let { return (header_output, decoder_output, exec_output, decode_block) }}; -def format BlockLoad(code, *opt_flags) {{ - # We need to make sure to check the highest priority fault last. - # That way, if other faults have been detected, they'll be overwritten - # rather than the other way around. - faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck - (header_output, - decoder_output, - exec_output, - decode_block) = doBlockMemFormat(code, faultCode, - LoadFuncs, name, Name, opt_flags) +def format BlockLoad(code, asi, *opt_flags) {{ + # We need to make sure to check the highest priority fault last. + # That way, if other faults have been detected, they'll be overwritten + # rather than the other way around. + faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck + (header_output, + decoder_output, + exec_output, + decode_block) = doBlockMemFormat(code, faultCode, - LoadExecute, name, Name, asi, opt_flags) ++ LoadFuncs, name, Name, asi, opt_flags) }}; -def format BlockStore(code, *opt_flags) {{ - # We need to make sure to check the highest priority fault last. - # That way, if other faults have been detected, they'll be overwritten - # rather than the other way around. - faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck - (header_output, - decoder_output, - exec_output, - decode_block) = doBlockMemFormat(code, faultCode, - StoreFuncs, name, Name, opt_flags) +def format BlockStore(code, asi, *opt_flags) {{ + # We need to make sure to check the highest priority fault last. + # That way, if other faults have been detected, they'll be overwritten + # rather than the other way around. + faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck + (header_output, + decoder_output, + exec_output, + decode_block) = doBlockMemFormat(code, faultCode, - StoreExecute, name, Name, asi, opt_flags) ++ StoreFuncs, name, Name, asi, opt_flags) }}; diff --cc src/arch/sparc/isa/formats/mem/util.isa index 3e9fd7a7d,e87223000..03b08ae18 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@@ -310,21 -318,10 +321,11 @@@ let { //and in the other they're distributed across two. Also note that for //execute functions, the name of the base class doesn't matter. let {{ - def doSplitExecute(code, execute, name, Name, asi, opt_flags, microParam): - def doSplitExecute(execute, name, Name, opt_flags, microParam): ++ def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): + microParam["asi_val"] = asi; - codeParam = microParam.copy() - codeParam["ea_code"] = '' - codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam) - eaIop = InstObjParams(name, Name, '', microParam["ea_code"], - opt_flags, microParam) - iop = InstObjParams(name, Name, '', code, opt_flags, microParam) - (iop.ea_decl, - iop.ea_rd, - iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb) - (iop.code_decl, - iop.code_rd, - iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb) - return execute.subst(iop) + iop = InstObjParams(name, Name, '', microParam, opt_flags) + (execf, initf, compf) = execute + return execf.subst(iop) + initf.subst(iop) + compf.subst(iop) def doDualSplitExecute(code, eaRegCode, eaImmCode, execute, @@@ -333,8 -330,9 +334,9 @@@ for (eaCode, name, Name) in ( (eaRegCode, nameReg, NameReg), (eaImmCode, nameImm, NameImm)): - microParams = {"ea_code" : eaCode, "fault_check": faultCode} - executeCode += doSplitExecute(code, execute, name, Name, + microParams = {"code": code, "ea_code": eaCode, + "fault_check": faultCode} + executeCode += doSplitExecute(execute, name, Name, - opt_flags, microParams) + asi, opt_flags, microParams) return executeCode }}; diff --cc src/arch/sparc/miscregfile.cc index 53559c072,50a4f4871..6641d38bb --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@@ -46,15 -50,15 +46,9 @@@ class Checkpoint string SparcISA::getMiscRegName(RegIndex index) { static::string miscRegName[NumMiscRegs] = - {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic", - "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", - "stick", "stick_cmpr", - "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", - "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", - "wstate", "gl", - "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", - "hstick_cmpr", - "fsr"}; + {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", - "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", - "stick", "stick_cmpr", - "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", + "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", + "wstate",*/ "gl", - "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", - "hstick_cmpr", - "fsr"}; return miscRegName[index]; } diff --cc src/cpu/exetrace.cc index 3fe40b4c1,780a0c4f7..98e75d83a --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@@ -385,18 -381,26 +391,26 @@@ Trace::InstRecord::dump(ostream &outs diffPil = true; if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP)) diffCwp = true; - if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE)) + //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE)) + if(shared_data->cansave != + thread->readIntReg(NumIntArchRegs + 3)) diffCansave = true; + //if(shared_data->canrestore != + // thread->readMiscReg(MISCREG_CANRESTORE)) if(shared_data->canrestore != - thread->readMiscReg(MISCREG_CANRESTORE)) + thread->readMiscReg(NumIntArchRegs + 4)) diffCanrestore = true; - if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN)) + //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN)) + if(shared_data->otherwin != + thread->readIntReg(NumIntArchRegs + 5)) diffOtherwin = true; - if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) + //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) + if(shared_data->cleanwin != + thread->readMiscReg(NumIntArchRegs + 6)) diffCleanwin = true; - if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc || - diffTstate || diffTt || diffHpstate || + if ((diffPC || diffCC || diffInst || diffRegs || diffTpc || + diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || diffPstate || diffY || diffCcr || diffTl || diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || diff --cc src/cpu/o3/iew_impl.hh index 76047b295,24c8484b4..70200d648 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@@ -514,7 -525,9 +525,10 @@@ DefaultIEW::squashDueToMemOrder(D toCommit->squash[tid] = true; toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->nextPC[tid] = inst->readNextPC(); + #if ISA_HAS_DELAY_SLOT + toCommit->nextNPC[tid] = inst->readNextNPC(); + #endif + toCommit->branchMispredict[tid] = false; toCommit->includeSquashInst[tid] = false; @@@ -531,7 -544,9 +545,10 @@@ DefaultIEW::squashDueToMemBlocked toCommit->squash[tid] = true; toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->nextPC[tid] = inst->readPC(); + #if ISA_HAS_DELAY_SLOT + toCommit->nextNPC[tid] = inst->readNextNPC(); + #endif + toCommit->branchMispredict[tid] = false; // Must include the broadcasted SN in the squash. toCommit->includeSquashInst[tid] = true;