From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 27 Nov 2018 04:28:28 +0000 (+0000)
Subject: move handle trap out to separate module, bit messy
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d0cd911291679429b039b653f0926cd160f475e;p=rv32.git

move handle trap out to separate module, bit messy
---

diff --git a/cpu.py b/cpu.py
index 7c8d2f3..fac67d4 100644
--- a/cpu.py
+++ b/cpu.py
@@ -235,54 +235,6 @@ class CPU(Module):
     #    return [m.mcause.eq(0),
     #            ]
 
-    def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
-        s = [ms.mpie.eq(ms.mie),
-             ms.mie.eq(0),
-             m.mepc.eq(Mux(ft.action == FA.noerror_trap,
-                           ft.output_pc + 4,
-                           ft.output_pc))]
-
-        # fetch action ack trap
-        i = If(ft.action == FA.ack_trap,
-                m.mcause.eq(cause_instruction_access_fault)
-              )
-
-        # ecall/ebreak
-        i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
-                m.mcause.eq(Mux(dc.immediate[0],
-                                cause_machine_environment_call,
-                                cause_breakpoint))
-              )
-
-        # load
-        i = i.Elif((dc.act & DA.load) != 0,
-                If(load_store_misaligned,
-                    m.mcause.eq(cause_load_address_misaligned)
-                ).Else(
-                    m.mcause.eq(cause_load_access_fault)
-                )
-              )
-
-        # store
-        i = i.Elif((dc.act & DA.store) != 0,
-                If(load_store_misaligned,
-                    m.mcause.eq(cause_store_amo_address_misaligned)
-                ).Else(
-                    m.mcause.eq(cause_store_amo_access_fault)
-                )
-              )
-
-        # jal/jalr -> misaligned=error, otherwise jump
-        i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
-                m.mcause.eq(cause_instruction_address_misaligned)
-              )
-
-        # defaults to illegal instruction
-        i = i.Else(m.mcause.eq(cause_illegal_instruction))
-
-        s.append(i)
-        return s
-
     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
                          ft, dc,
                          load_store_misaligned,
@@ -290,15 +242,18 @@ class CPU(Module):
                          lui_auipc_result):
         c = {}
         c[FOS.empty] = []
-        c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
-                                       load_store_misaligned)
+        c[FOS.trap] = self.handle_trap.eq(1)
         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
                                        mstatus, mie, ft, dc,
                                        load_store_misaligned,
                                        loaded_value,
                                        alu_result,
                                        lui_auipc_result)
-        return Case(ft.output_state, c)
+        return [self.handle_trap.eq(0),
+                self.regs.w_en.eq(0),
+                Case(ft.output_state, c),
+                self.handle_trap.eq(0),
+                self.regs.w_en.eq(0)]
 
     def write_register(self, rd, val):
         return [self.regs.rd.eq(rd),
@@ -313,8 +268,7 @@ class CPU(Module):
                            lui_auipc_result):
         # fetch action ack trap
         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
-                [self.handle_trap(m, mstatus, ft, dc,
-                                       load_store_misaligned),
+                [self.handle_trap.eq(1),
                  self.regs.w_en.eq(0) # no writing to registers
                 ]
               )
@@ -665,6 +619,20 @@ class CPU(Module):
 
         minfo = MInfo(self.comb)
 
+        self.handle_trap = Signal(reset=0)
+
+        ht = Instance("CPUHandleTrap", "cpu_handle_trap",
+                      i_ft_action = ft.action,
+                      i_ft_output_pc = ft.output_pc,
+                      i_dc_action = dc.act,
+                      i_dc_immediate = dc.immediate,
+                      i_load_store_misaligned = load_store_misaligned,
+                      o_mcause = m.mcause,
+                      o_mepc = m.mepc,
+                      o_mie = mstatus.mie)
+
+        self.specials += ht
+
         self.sync += If(~self.reset,
                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
                                         mstatus, mie, ft, dc,
diff --git a/cpu_handle_trap.py b/cpu_handle_trap.py
index c77be86..eaf3daf 100644
--- a/cpu_handle_trap.py
+++ b/cpu_handle_trap.py
@@ -45,6 +45,7 @@ class CPUHandleTrap(Module):
         self.reset = ResetSignal()
 
         self.handle_trap = Signal()
+        self.trap_handled = Signal()
         self.ft_action = Signal(fetch_action)
         self.dc_action = Signal(decode_action)
         self.dc_immediate = Signal(32)
@@ -101,7 +102,11 @@ class CPUHandleTrap(Module):
 
         s.append(i)
 
-        self.sync += If(self.handle_trap, s)
+        self.sync += If(self.handle_trap,
+                        [s, self.trap_handled.eq(1)]
+                     ).Else(
+                        self.trap_handled.eq(0)
+                     )
 
 
 if __name__ == "__main__":
@@ -109,6 +114,7 @@ if __name__ == "__main__":
     print(verilog.convert(example,
          {
             example.handle_trap,
+            example.trap_handled,
             example.ft_action,
             example.dc_immediate,
             example.mcause,