From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Nov 2021 21:38:42 +0000 (+0000)
Subject: add debug prints in old simulator
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d1fc5a823d98770988111603052e0fff31d63b0;p=soc.git

add debug prints in old simulator
---

diff --git a/src/soc/experiment/cscore.py b/src/soc/experiment/cscore.py
index ea6bd320..b6618478 100644
--- a/src/soc/experiment/cscore.py
+++ b/src/soc/experiment/cscore.py
@@ -265,8 +265,12 @@ class RegSim:
         src2 = self.regs[src2]
         if op == IADD:
             val = (src1 + src2) & ((1 << (self.rwidth))-1)
+            print ("RegSim op: ADD", hex(src1), hex(src2), hex(val))
         elif op == ISUB:
             val = (src1 - src2) & ((1 << (self.rwidth))-1)
+            print ("RegSim op: SUB", hex(src1), hex(src2), hex(val))
+        else:
+            print ("RegSim op: UNSUPPORTED", op)
         self.regs[dest] = val
 
     def setval(self, dest, val):