From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 9 Mar 2022 12:12:51 +0000 (+0000)
Subject: add stall signal to arbiter, assume nmigen-soc takes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d278400b01d75fbb4cae435292f632dd6292016;p=ls2.git

add stall signal to arbiter, assume nmigen-soc takes
care of adaptation from WB4-pipeline-burst to WB3-classic
---

diff --git a/src/ls2.py b/src/ls2.py
index e6cc8bf..76cebdc 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -8,7 +8,7 @@
 # under EU Grants 871528 and 957073, under the LGPLv3+ License
 
 from nmigen import (Module, Elaboratable, DomainRenamer, Record,
-                    Signal, Cat, Const)
+                    Signal, Cat, Const, ClockSignal, ResetSignal)
 from nmigen.cli import verilog
 from nmigen.lib.cdc import ResetSynchronizer
 from nmigen_soc import wishbone, memory
@@ -150,8 +150,6 @@ class WB64to32Convert(Elaboratable):
                 if hasattr(slave, "stall"):
                     with m.If(~slave.stall):
                         sync += slave.stb.eq(0)
-                else:
-                    sync += slave.stb.eq(0)
 
                 # Handle ack
                 with m.If(slave.ack):
@@ -176,6 +174,7 @@ class WB64to32Convert(Elaboratable):
                     with m.Else():
                         # We are done, ack up, clear cyc downstram
                         sync += slave.cyc.eq(0)
+                        sync += slave.stb.eq(0)
 
                         # And ack & unstall upstream
                         sync += master.ack.eq(1)
@@ -190,7 +189,6 @@ class WB64to32Convert(Elaboratable):
                 if hasattr(slave, "stall"):
                     with m.If(~slave.stall):
                         sync += slave.stb.eq(0)
-                else:
                     sync += slave.stb.eq(0)
 
                 # Handle ack
@@ -201,10 +199,11 @@ class WB64to32Convert(Elaboratable):
 
                     # We are done, ack up, clear cyc downstram
                     sync += slave.cyc.eq(0)
+                    sync += slave.stb.eq(0)
 
                     # And ack & unstall upstream
                     sync += master.ack.eq(1)
-                    if hasattr(master , "stall"):
+                    if hasattr(master, "stall"):
                         sync += master.stall.eq(0)
 
                     # Wait for next one
@@ -224,14 +223,31 @@ class DDR3SoC(SoC, Elaboratable):
                  clk_freq=50e6,
                  add_cpu=True):
 
+        # wishbone routing is as follows:
+        #
+        #         SoC
+        #       +--+--+
+        #       |     |
+        #      ibus  dbus
+        #       |     |
+        #       +--+--+
+        #          | 
+        #      64to32DownCvt
+        #          |
+        #       arbiter
+        #          |
+        #   +---decoder----+--------+
+        #   |      |       |        |
+        #  uart  XICS    CSRs     DRAM
+
         # set up wishbone bus arbiter and decoder. arbiter routes,
         # decoder maps local-relative addressed satellites to global addresses
         self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32,
                                          granularity=8,
-                                         features={"cti", "bte"})
+                                         features={"cti", "bte", "stall"})
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32,
                                          granularity=8,
-                                         features={"cti", "bte"})
+                                         features={"cti", "bte", "stall"})
 
         # default firmware name
         if firmware is None:
@@ -244,13 +260,15 @@ class DDR3SoC(SoC, Elaboratable):
         if add_cpu:
             self.cpu = ExternalCore(name="ext_core")
             cvtdbus = wishbone.Interface(addr_width=30, data_width=32,
-                                         granularity=8)
+                                         granularity=8, features={'stall'})
             cvtibus = wishbone.Interface(addr_width=30, data_width=32,
-                                         granularity=8)
+                                         granularity=8, features={'stall'})
             self.dbusdowncvt = WB64to32Convert(self.cpu.dbus, cvtdbus)
             self.ibusdowncvt = WB64to32Convert(self.cpu.ibus, cvtibus)
             self._arbiter.add(cvtibus) # I-Cache Master
             self._arbiter.add(cvtdbus) # D-Cache Master. TODO JTAG master
+            self.cvtibus = cvtibus
+            self.cvtdbus = cvtdbus
 
             # CPU interrupt controller
             self.intc = GenericInterruptController(width=len(self.cpu.irq))
@@ -372,6 +390,7 @@ class DDR3SoC(SoC, Elaboratable):
             comb += uartbus.adr.eq(self.cvtuartbus.adr)
             comb += uartbus.stb.eq(self.cvtuartbus.stb)
             comb += uartbus.cyc.eq(self.cvtuartbus.cyc)
+            comb += uartbus.sel.eq(self.cvtuartbus.sel)
             comb += uartbus.we.eq(self.cvtuartbus.we)
             comb += uartbus.dat_w.eq(self.cvtuartbus.dat_w) # drops 8..31
             comb += self.cvtuartbus.dat_r.eq(uartbus.dat_r) # drops 8..31
@@ -382,7 +401,7 @@ class DDR3SoC(SoC, Elaboratable):
             m.submodules.dbuscvt = self.dbusdowncvt
             m.submodules.ibuscvt = self.ibusdowncvt
             # create stall sigs, assume wishbone classic
-            #ibus, dbus = self.cpu.ibus, self.cpu.dbus
+            #ibus, dbus = self.cvtibus, self.cvtdbus
             #comb += ibus.stall.eq(ibus.stb & ~ibus.ack)
             #comb += dbus.stall.eq(dbus.stb & ~dbus.ack)
 
@@ -444,7 +463,7 @@ class DDR3SoC(SoC, Elaboratable):
                 for phase in self.dramcore.dfii._inti.phases:
                     print ("dfi master", phase)
                     ports += list(phase.fields.values())
-        ports += [ClockSignal(), ClockSignal("dramsync"), ResetSignal()]
+        ports += [ClockSignal(), ResetSignal()]
         return ports
 
 if __name__ == "__main__":