From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Jun 2019 15:22:22 +0000 (-0700)
Subject: More accurate CHANGELOG
X-Git-Tag: working-ls180~1237^2~132
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d34cea65af5b34ce0930fb892fca6742db898ab;p=yosys.git

More accurate CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index 6e3faa9ff..139f71672 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -17,7 +17,9 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "rename -src"
     - Added "equiv_opt" pass
     - Added "read_aiger" frontend
-    - Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9)
+    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+    - Added "synth_xilinx -abc9" (experimental)
+    - Added "synth_ice40 -abc9" (experimental)
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"