From: Andreas Sandberg <Andreas.Sandberg@ARM.com>
Date: Thu, 16 Oct 2014 09:49:41 +0000 (-0400)
Subject: arm: Add TLB PMU probes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d35d48e848914fd6cf18b016cb9125c50e422c0;p=gem5.git

arm: Add TLB PMU probes

This changeset adds probe points that can be used to implement PMU
counters for TLB stats. The following probes are supported:

* ArmISA::TLB::ppRefills / TLB Refills (TLB insertions)
---

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 94343c1c2..7f296e7cf 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -197,6 +197,7 @@ TLB::insert(Addr addr, TlbEntry &entry)
     table[0] = entry;
 
     inserts++;
+    ppRefills->notify(1);
 }
 
 void
@@ -531,6 +532,12 @@ TLB::regStats()
     accesses = readAccesses + writeAccesses + instAccesses;
 }
 
+void
+TLB::regProbePoints()
+{
+    ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills"));
+}
+
 Fault
 TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
                  Translation *translation, bool &delay, bool timing)
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index b9025fa5f..06a51e5da 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -53,6 +53,7 @@
 #include "mem/request.hh"
 #include "params/ArmTLB.hh"
 #include "sim/fault_fwd.hh"
+#include "sim/probe/pmu.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
@@ -131,6 +132,9 @@ class TLB : public BaseTLB
     Stats::Formula misses;
     Stats::Formula accesses;
 
+    /** PMU probe for TLB refills */
+    ProbePoints::PMUUPtr ppRefills;
+
     int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
 
     bool bootUncacheability;
@@ -291,6 +295,8 @@ class TLB : public BaseTLB
 
     void regStats();
 
+    void regProbePoints() M5_ATTR_OVERRIDE;
+
     /**
      * Get the table walker master port. This is used for migrating
      * port connections during a CPU takeOverFrom() call. For