From: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
Date: Thu, 14 Feb 2019 08:53:21 +0000 (+0100)
Subject: Turned the add_1 verilog state into nmigen
X-Git-Tag: ls180-24jan2020~2021
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d3ef49cdd08c4ffb9c82063857bc918a2add954;p=ieee754fpu.git

Turned the add_1 verilog state into nmigen
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 5eb20770..9437eb43 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -208,6 +208,26 @@ class FPADD:
                         tot.eq(b_m - a_m),
                         z_s.eq(b_s)
                 ]
+
+            with m.State("add_1"):
+                m.next = "normalise_1"
+
+                with m.If(tot[27]):
+                    m.d.sync += [
+                        z_m.eq(tot[4:27]),
+                        guard.eq(tot[3]),
+                        round_bit.eq(tot[2]),
+                        sticky.eq(tot[1] | tot[0]),
+                        z_e.eq(z_e + 1)
+                ]
+
+                with m.Else():
+                    m.d.sync += [
+                        z_m.eq(tot[3:26]),
+                        guard.eq(tot[2]),
+                        round_bit.eq(tot[1]),
+                        sticky.eq(tot[0])
+                ]
         return m
 
 """