From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 15 Feb 2024 04:32:43 +0000 (-0800)
Subject: test/bigint/mul_remap: fill in some svremap instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d45047d7e7bc8678cd3ea30e1e883249f1fa344;p=openpower-isa.git

test/bigint/mul_remap: fill in some svremap instructions
---

diff --git a/src/openpower/test/bigint/mul_remap.py b/src/openpower/test/bigint/mul_remap.py
index 2f59f25a..4baaba8f 100644
--- a/src/openpower/test/bigint/mul_remap.py
+++ b/src/openpower/test/bigint/mul_remap.py
@@ -77,10 +77,13 @@ def mul_remap_256_x_256_to_512_asm():
     ]
     retval += [
         "loop:",
-        # FIXME: use SVSHAPE0 for RA, SVSHAPE1 for RB,
+        # use SVSHAPE0 for RA, SVSHAPE1 for RB,
         # SVSHAPE2 for RC/RT, SVSHAPE3 for RS
-        "sv.maddedu *4, *32, *36, *4",  # RS is scalar by using constant remap
-        # FIXME: use SVSHAPE2 for RT/RA
+        "svremap 0o37, 0, 1, 2, 2, 3, 0",
+        # RS is scalar by using constant remap
+        "sv.maddedu *4, *32, *36, *4",  # FIXME: need to set EXTRA2_MODE to 0
+        # use SVSHAPE2 for RT/RA, all others are not remapped
+        "svremap 0o11, 2, 0, 0, 2, 0, 0",
         "sv.adde *5, *5, 20",  # FIXME: maddedu's RS is in r20, right?
         "svstep 0, 0, 1",
         "bc 16, 0, loop # bdnz loop",