From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Sep 2020 18:06:37 +0000 (+0100)
Subject: reduce XICS address lookup by 2 bits
X-Git-Tag: semi_working_ecp5~181
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d4e6cfeaf200bd4870989242ae9f6bede65b710;p=soc.git

reduce XICS address lookup by 2 bits
---

diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py
index 7abd2e95..1b6b95fd 100644
--- a/src/soc/interrupts/xics.py
+++ b/src/soc/interrupts/xics.py
@@ -117,7 +117,7 @@ class XICS_ICP(Elaboratable):
             comb += v.wb_ack.eq(1) # always ack
             with m.If(self.bus.we): # write
                 # writes to both XIRR are the same
-                with m.Switch(self.bus.adr[:8]):
+                with m.Switch(self.bus.adr[:6]):
                     with m.Case(XIRR_POLL):
                         # report "ICP XIRR_POLL write";
                         comb += v.cppr.eq(be_in[24:32])
@@ -151,7 +151,7 @@ class XICS_ICP(Elaboratable):
 
             with m.Else(): # read
 
-                with m.Switch(self.bus.adr[:8]):
+                with m.Switch(self.bus.adr[:6]):
                     with m.Case(XIRR_POLL):
                         # report "ICP XIRR_POLL read";
                         comb += be_out.eq(r.xisr & r.cppr)