From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jun 2020 19:19:14 +0000 (+0100)
Subject: add readonly option to TestMemory
X-Git-Tag: div_pipeline~217
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d69e91e8baa66366a9f36093b738a25dc126659;p=soc.git

add readonly option to TestMemory
---

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 02000d89..bf7c7e3b 100644
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -2,7 +2,9 @@ from nmigen import Module, Elaboratable, Memory
 
 
 class TestMemory(Elaboratable):
-    def __init__(self, regwid, addrw, granularity=None, init=True):
+    def __init__(self, regwid, addrw, granularity=None, init=True,
+                                      readonly=False):
+        self.readonly = readonly
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
         self.depth = depth
@@ -14,11 +16,15 @@ class TestMemory(Elaboratable):
             init = None
         self.mem = Memory(width=regwid, depth=depth, init=init)
         self.rdport = self.mem.read_port() # not now transparent=False)
+        if self.readonly:
+            return
         self.wrport = self.mem.write_port(granularity=granularity)
 
     def elaborate(self, platform):
         m = Module()
         m.submodules.rdport = self.rdport
+        if self.readonly:
+            return m
         m.submodules.wrport = self.wrport
         return m
 
@@ -26,6 +32,8 @@ class TestMemory(Elaboratable):
         yield self.rdport.addr
         yield self.rdport.data
         #yield self.rdport.en
+        if self.readonly:
+            return
         yield self.wrport.addr
         yield self.wrport.data
         yield self.wrport.en