From: lkcl <lkcl@web>
Date: Sun, 24 Jul 2022 22:28:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1044
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d8a797103568d98ff15c473e6780195612fbbe3;p=libreriscv.git

---

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index ced048274..f0e2ca470 100644
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -7,6 +7,12 @@ allocation of opcodes (five) to implement, whereas any other Vector
 implementation would require an intrusive fundamental overhaul of the
 Power ISA.
 
+*If not done as carefully as SVP64, the addition of any other Scalable
+Vector Extension would require a significant number of opcodes, putting
+further pressure on Major Opcode space which was never designed with
+Scalable Vectors in mind in the first place.  Contrast with RISC-V which was
+designed over a 7 year period with Cray-style Vectors right from the start.*
+
 It is extremely important to think of Simple-V as a 2-Dimensional ISA:
 instructions vertical and registers horizontal otherwise it will be
 difficult to grasp and appreciate its RISC simplicity.