From: lkcl <lkcl@web>
Date: Mon, 8 May 2023 16:48:51 +0000 (+0100)
Subject: spelling
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d9782084a3dc37ed9247e26565cf732de61b265;p=libreriscv.git

spelling
---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index c159e0fc6..5b584079c 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -998,7 +998,7 @@ they are different SV regs.
 
 * `rlwimi RA, RS, ...`
 * Rsrc1_EXTRA3 applies to RS as the first src
-* Rsrc2_EXTRA3 applies to RA as the secomd src
+* Rsrc2_EXTRA3 applies to RA as the second src
 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
 
 With the addition of the EXTRA bits, the three registers
@@ -1034,7 +1034,7 @@ single-predicate, three registers (2 read, 1 write)
 ### RM-2P-2S1D/1S2D/3S
 
 The primary purpose for this encoding is for Twin Predication on LOAD
-and STORE operations.  see [[sv/ldst]] for detailed anslysis.
+and STORE operations.  see [[sv/ldst]] for detailed analysis.
 
 **RM-2P-2S1D:**