From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Wed, 4 Nov 2020 00:58:45 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1873
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d97e7babb3d2e49ec8f11be8b93d57753b535f8;p=libreriscv.git

---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index d966dc567..80dca134a 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -155,7 +155,7 @@ and therefore have no value are marked with 'NOT'
 
 ## Images of wires on FPGA and on STLINKV2
 
-[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="200x" ]]                                    
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="250x" ]]                                    
 
 ## Questions