From: Earl Ou <shunhsingou@google.com>
Date: Wed, 27 Jan 2021 08:24:09 +0000 (+0800)
Subject: fastmodel: remove incorrect cntfrq update
X-Git-Tag: develop-gem5-snapshot~179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9d98439ca0c9294dc7755594c48f123b734f0979;p=gem5.git

fastmodel: remove incorrect cntfrq update

The register cntfrq should be set to system counter frequency.
However, the current fastmodel implementation accidentally set it to
core frequency. This CL removes the wrong implementation, and real
cntfrq setting is performed in the initState.

Change-Id: I6c62822a4fbbcc0c499f79f6003dabb0c133f997
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40276
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
index 68ff1a80d..724b04d4f 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -66,19 +66,6 @@ class CortexA76 : public Iris::CPU<CortexA76TC>
         Base(p, scx::scx_get_iris_connection_interface()), _params(p)
     {}
 
-    void
-    clockPeriodUpdated() override
-    {
-        Base::clockPeriodUpdated();
-
-        // FIXME(b/139447397): this is a workaround since CNTFRQ_EL0 should not
-        // be modified after clock is changed in real hardwares. Remove or
-        // modify this after a more reasonable solution is found.
-        for (auto *tc : threadContexts) {
-            tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, frequency());
-        }
-    }
-
     void initState() override;
 
     template <class T>