From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 16 Dec 2019 10:12:38 +0000 (+0100)
Subject: build/xilinx/XilinxMultiRegImpl: fix n=0 case
X-Git-Tag: 24jan2021_ls180~806
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9da28c4ea51c466ca6c19747877d9de2b0704ad7;p=litex.git

build/xilinx/XilinxMultiRegImpl: fix n=0 case
---

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index dffe5872..8848d85c 100644
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -78,7 +78,8 @@ class XilinxMultiRegImpl(MultiRegImpl):
         if not hasattr(i, "attr"):
             i0, i = i, Signal()
             self.comb += i.eq(i0)
-        self.regs[0].attr.add("mr_ff")
+        if len(self.regs):
+            self.regs[0].attr.add("mr_ff")
         for r in self.regs:
             r.attr.add("async_reg")
             r.attr.add("no_shreg_extract")