From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 6 Mar 2012 14:26:04 +0000 (+0100)
Subject: sim: VCD generation
X-Git-Tag: 24jan2021_ls180~2099^2~993
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9da512dbf5effc90a0c2a867f3a1e387250f8fa4;p=litex.git

sim: VCD generation
---

diff --git a/examples/basic_sim.py b/examples/basic_sim.py
index 55db802c..17860723 100644
--- a/examples/basic_sim.py
+++ b/examples/basic_sim.py
@@ -1,5 +1,5 @@
 from migen.fhdl.structure import *
-from migen.sim.generic import Simulator
+from migen.sim.generic import Simulator, TopLevel
 from migen.sim.icarus import Runner
 
 class Counter:
@@ -21,7 +21,7 @@ class Counter:
 
 def main():
 	dut = Counter()
-	sim = Simulator(dut.get_fragment(), Runner())
+	sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
 	sim.run(10)
 
 main()
diff --git a/migen/sim/generic.py b/migen/sim/generic.py
index db9978a6..79607b24 100644
--- a/migen/sim/generic.py
+++ b/migen/sim/generic.py
@@ -3,8 +3,11 @@ from migen.fhdl import verilog
 from migen.sim.ipc import *
 
 class TopLevel:
-	def __init__(self, top_name="top", dut_type="dut", dut_name="dut", clk_name="sys_clk", 
-	  clk_period=10, rst_name="sys_rst"):
+	def __init__(self, vcd_name=None, vcd_level=1,
+	  top_name="top", dut_type="dut", dut_name="dut",
+	  clk_name="sys_clk", clk_period=10, rst_name="sys_rst"):
+		self.vcd_name = vcd_name
+		self.vcd_level = vcd_level
 		self.top_name = top_name
 		self.dut_type = dut_type
 		self.dut_name = dut_name
@@ -13,7 +16,9 @@ class TopLevel:
 		self.rst_name = rst_name
 	
 	def get(self, sockaddr):
-		template = """module {top_name}();
+		template1 = """`timescale 1ns / 1ps
+
+module {top_name}();
 
 reg {clk_name};
 reg {rst_name};
@@ -38,16 +43,26 @@ end
 
 initial $migensim_connect("{sockaddr}");
 always @(posedge {clk_name}) $migensim_tick;
-
-endmodule
 """
-		return template.format(top_name=self.top_name,
+		template2 = """
+initial begin
+	$dumpfile("{vcd_name}");
+	$dumpvars({vcd_level}, {dut_name});
+end
+"""
+		r = template1.format(top_name=self.top_name,
 			dut_type=self.dut_type,
 			dut_name=self.dut_name,
 			clk_name=self.clk_name,
 			hclk_period=str(self.clk_period/2),
 			rst_name=self.rst_name,
 			sockaddr=sockaddr)
+		if self.vcd_name is not None:
+			r += template2.format(vcd_name=self.vcd_name,
+				vcd_level=str(self.vcd_level),
+				dut_name=self.dut_name)
+		r += "\nendmodule"
+		return r
 
 class Simulator:
 	def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket"):